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Microblaze cacheline length is configurable and current cpu uses two cacheline length 4 and 8. We are taking conservative maximum value to be sure that cacheline alignment is satisfied for all cases. Here is the calculation for cacheline lenght 8 32bit=4Byte values which is corresponding with SHIFT 5. Signed-off-by: Michal Simek <monstr@monstr.eu>
25 lines
644 B
C
25 lines
644 B
C
/*
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* Cache operations
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#ifndef _ASM_MICROBLAZE_CACHE_H
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#define _ASM_MICROBLAZE_CACHE_H
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#include <asm/registers.h>
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#define L1_CACHE_SHIFT 5
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/* word-granular cache in microblaze */
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#endif /* _ASM_MICROBLAZE_CACHE_H */
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