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https://github.com/edk2-porting/linux-next.git
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a6dbba77a9
This patch adds on-chip PCI bridge support for the PQ2 family. The incomplete existent code is updated with interrupt handling stuff and board-specific bits for 8272ADS and PQ2FADS; the related files were renamed (from m8260_pci to m82xx_pci) to be of more generic fashion. This is tested with 8266ADS and 8272ADS, should work on PQ2FADS as well. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/*
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* A collection of structures, addresses, and values associated with
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* the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
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* Copied from the RPX-Classic and SBS8260 stuff.
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*
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* Copyright (c) 2001 Dan Malek (dan@mvista.com)
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*/
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#ifdef __KERNEL__
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#ifndef __MACH_ADS8260_DEFS
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#define __MACH_ADS8260_DEFS
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#include <linux/config.h>
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#include <asm/ppcboot.h>
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/* Memory map is configured by the PROM startup.
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* We just map a few things we need. The CSR is actually 4 byte-wide
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* registers that can be accessed as 8-, 16-, or 32-bit values.
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*/
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#define CPM_MAP_ADDR ((uint)0xf0000000)
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#define BCSR_ADDR ((uint)0xf4500000)
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#define BCSR_SIZE ((uint)(32 * 1024))
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#define BOOTROM_RESTART_ADDR ((uint)0xff000104)
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/* For our show_cpuinfo hooks. */
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#define CPUINFO_VENDOR "Motorola"
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#define CPUINFO_MACHINE "PQ2 ADS PowerPC"
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/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
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* only on word boundaries.
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* Not all are used (yet), or are interesting to us (yet).
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*/
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/* Things of interest in the CSR.
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*/
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#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
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#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
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#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable */
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#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
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#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 == enable */
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#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 == enable */
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#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable */
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#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
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#define PHY_INTERRUPT SIU_INT_IRQ7
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#ifdef CONFIG_PCI
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/* PCI interrupt controller */
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#define PCI_INT_STAT_REG 0xF8200000
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#define PCI_INT_MASK_REG 0xF8200004
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#define PIRQA (NR_CPM_INTS + 0)
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#define PIRQB (NR_CPM_INTS + 1)
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#define PIRQC (NR_CPM_INTS + 2)
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#define PIRQD (NR_CPM_INTS + 3)
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/*
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* PCI memory map definitions for MPC8266ADS-PCI.
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*
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* processor view
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* local address PCI address target
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* 0x80000000-0x9FFFFFFF 0x80000000-0x9FFFFFFF PCI mem with prefetch
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* 0xA0000000-0xBFFFFFFF 0xA0000000-0xBFFFFFFF PCI mem w/o prefetch
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* 0xF4000000-0xF7FFFFFF 0x00000000-0x03FFFFFF PCI IO
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*
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* PCI master view
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* local address PCI address target
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* 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
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*/
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/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
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Here we should redefine what is unique for this board */
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#define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */
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#define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */
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#define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */
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#define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */
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#define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */
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#if defined(CONFIG_ADS8272)
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#define PCI_INT_TO_SIU SIU_INT_IRQ2
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#elif defined(CONFIG_PQ2FADS)
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#define PCI_INT_TO_SIU SIU_INT_IRQ6
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#else
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#warning PCI Bridge will be without interrupts support
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#endif
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#endif /* CONFIG_PCI */
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#endif /* __MACH_ADS8260_DEFS */
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#endif /* __KERNEL__ */
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