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1077fa36f2
There are a number of situations where the mandatory barriers rmb() and wmb() are used to order memory/memory operations in the device drivers and those barriers are much heavier than they actually need to be. For example in the case of PowerPC wmb() calls the heavy-weight sync instruction when for coherent memory operations all that is really needed is an lsync or eieio instruction. This commit adds a coherent only version of the mandatory memory barriers rmb() and wmb(). In most cases this should result in the barrier being the same as the SMP barriers for the SMP case, however in some cases we use a barrier that is somewhere in between rmb() and smp_rmb(). For example on ARM the rmb barriers break down as follows: Barrier Call Explanation --------- -------- ---------------------------------- rmb() dsb() Data synchronization barrier - system dma_rmb() dmb(osh) data memory barrier - outer sharable smp_rmb() dmb(ish) data memory barrier - inner sharable These new barriers are not as safe as the standard rmb() and wmb(). Specifically they do not guarantee ordering between coherent and incoherent memories. The primary use case for these would be to enforce ordering of reads and writes when accessing coherent memory that is shared between the CPU and a device. It may also be noted that there is no dma_mb(). Most architectures don't provide a good mechanism for performing a coherent only full barrier without resorting to the same mechanism used in mb(). As such there isn't much to be gained in trying to define such a function. Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Cc: Michael Ellerman <michael@ellerman.id.au> Cc: Michael Neuling <mikey@neuling.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@kernel.org> Cc: David Miller <davem@davemloft.net> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
#ifndef _ASM_X86_BARRIER_H
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#define _ASM_X86_BARRIER_H
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#include <asm/alternative.h>
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#include <asm/nops.h>
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_X86_32
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/*
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* Some non-Intel clones support out of order store. wmb() ceases to be a
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* nop for these.
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*/
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#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
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#else
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#endif
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#ifdef CONFIG_X86_PPRO_FENCE
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#define dma_rmb() rmb()
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#else
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#define dma_rmb() barrier()
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#endif
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#define dma_wmb() barrier()
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() dma_rmb()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#else /* !SMP */
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif /* SMP */
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#define read_barrier_depends() do { } while (0)
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#define smp_read_barrier_depends() do { } while (0)
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#if defined(CONFIG_X86_PPRO_FENCE)
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/*
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* For this option x86 doesn't have a strong TSO memory
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* model and we should fall back to full barriers.
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*/
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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smp_mb(); \
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___p1; \
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})
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#else /* regular x86 TSO memory ordering */
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#define smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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ACCESS_ONCE(*p) = (v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = ACCESS_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#endif
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/* Atomic operations are already serializing on x86 */
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#define smp_mb__before_atomic() barrier()
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#define smp_mb__after_atomic() barrier()
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/*
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* Stop RDTSC speculation. This is needed when you need to use RDTSC
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* (or get_cycles or vread that possibly accesses the TSC) in a defined
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* code region.
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*
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* (Could use an alternative three way for this if there was one.)
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*/
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static __always_inline void rdtsc_barrier(void)
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{
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alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
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alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
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}
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#endif /* _ASM_X86_BARRIER_H */
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