mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 12:14:01 +08:00
e7cddda48c
This patch add USB client support Marvell PXA9xx/PXA168 chips. The USB controller in PXA9xx/PXA168 is a High-Speed OTG controller. The available endpoints is different between PXA9xx and PXA168. NOTE: It is the first version of Marvell PXA9xx/PXA168 USB controller driver. The support for OTG mode will be added in later patch. PXA9xx and PXA168 has integrated UTMI PHY in the chips. The initialization for the PHY is a little different between PXA9xx and PXA168. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
295 lines
8.9 KiB
C
295 lines
8.9 KiB
C
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#ifndef __MV_UDC_H
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#define __MV_UDC_H
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#define VUSBHS_MAX_PORTS 8
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#define DQH_ALIGNMENT 2048
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#define DTD_ALIGNMENT 64
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#define DMA_BOUNDARY 4096
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#define EP_DIR_IN 1
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#define EP_DIR_OUT 0
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#define DMA_ADDR_INVALID (~(dma_addr_t)0)
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#define EP0_MAX_PKT_SIZE 64
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/* ep0 transfer state */
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#define WAIT_FOR_SETUP 0
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#define DATA_STATE_XMIT 1
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#define DATA_STATE_NEED_ZLP 2
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#define WAIT_FOR_OUT_STATUS 3
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#define DATA_STATE_RECV 4
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#define CAPLENGTH_MASK (0xff)
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#define DCCPARAMS_DEN_MASK (0x1f)
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#define HCSPARAMS_PPC (0x10)
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/* Frame Index Register Bit Masks */
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#define USB_FRINDEX_MASKS 0x3fff
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/* Command Register Bit Masks */
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#define USBCMD_RUN_STOP (0x00000001)
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#define USBCMD_CTRL_RESET (0x00000002)
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#define USBCMD_SETUP_TRIPWIRE_SET (0x00002000)
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#define USBCMD_SETUP_TRIPWIRE_CLEAR (~USBCMD_SETUP_TRIPWIRE_SET)
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#define USBCMD_ATDTW_TRIPWIRE_SET (0x00004000)
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#define USBCMD_ATDTW_TRIPWIRE_CLEAR (~USBCMD_ATDTW_TRIPWIRE_SET)
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/* bit 15,3,2 are for frame list size */
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#define USBCMD_FRAME_SIZE_1024 (0x00000000) /* 000 */
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#define USBCMD_FRAME_SIZE_512 (0x00000004) /* 001 */
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#define USBCMD_FRAME_SIZE_256 (0x00000008) /* 010 */
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#define USBCMD_FRAME_SIZE_128 (0x0000000C) /* 011 */
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#define USBCMD_FRAME_SIZE_64 (0x00008000) /* 100 */
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#define USBCMD_FRAME_SIZE_32 (0x00008004) /* 101 */
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#define USBCMD_FRAME_SIZE_16 (0x00008008) /* 110 */
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#define USBCMD_FRAME_SIZE_8 (0x0000800C) /* 111 */
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#define EPCTRL_TX_ALL_MASK (0xFFFF0000)
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#define EPCTRL_RX_ALL_MASK (0x0000FFFF)
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#define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000)
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#define EPCTRL_TX_EP_STALL (0x00010000)
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#define EPCTRL_RX_EP_STALL (0x00000001)
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#define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040)
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#define EPCTRL_RX_ENABLE (0x00000080)
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#define EPCTRL_TX_ENABLE (0x00800000)
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#define EPCTRL_CONTROL (0x00000000)
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#define EPCTRL_ISOCHRONOUS (0x00040000)
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#define EPCTRL_BULK (0x00080000)
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#define EPCTRL_INT (0x000C0000)
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#define EPCTRL_TX_TYPE (0x000C0000)
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#define EPCTRL_RX_TYPE (0x0000000C)
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#define EPCTRL_DATA_TOGGLE_INHIBIT (0x00000020)
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#define EPCTRL_TX_EP_TYPE_SHIFT (18)
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#define EPCTRL_RX_EP_TYPE_SHIFT (2)
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#define EPCOMPLETE_MAX_ENDPOINTS (16)
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/* endpoint list address bit masks */
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#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
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#define PORTSCX_W1C_BITS 0x2a
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#define PORTSCX_PORT_RESET 0x00000100
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#define PORTSCX_PORT_POWER 0x00001000
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#define PORTSCX_FORCE_FULL_SPEED_CONNECT 0x01000000
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#define PORTSCX_PAR_XCVR_SELECT 0xC0000000
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#define PORTSCX_PORT_FORCE_RESUME 0x00000040
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#define PORTSCX_PORT_SUSPEND 0x00000080
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#define PORTSCX_PORT_SPEED_FULL 0x00000000
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#define PORTSCX_PORT_SPEED_LOW 0x04000000
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#define PORTSCX_PORT_SPEED_HIGH 0x08000000
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#define PORTSCX_PORT_SPEED_MASK 0x0C000000
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/* USB MODE Register Bit Masks */
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#define USBMODE_CTRL_MODE_IDLE 0x00000000
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#define USBMODE_CTRL_MODE_DEVICE 0x00000002
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#define USBMODE_CTRL_MODE_HOST 0x00000003
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#define USBMODE_CTRL_MODE_RSV 0x00000001
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#define USBMODE_SETUP_LOCK_OFF 0x00000008
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#define USBMODE_STREAM_DISABLE 0x00000010
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/* USB STS Register Bit Masks */
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#define USBSTS_INT 0x00000001
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#define USBSTS_ERR 0x00000002
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#define USBSTS_PORT_CHANGE 0x00000004
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#define USBSTS_FRM_LST_ROLL 0x00000008
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#define USBSTS_SYS_ERR 0x00000010
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#define USBSTS_IAA 0x00000020
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#define USBSTS_RESET 0x00000040
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#define USBSTS_SOF 0x00000080
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#define USBSTS_SUSPEND 0x00000100
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#define USBSTS_HC_HALTED 0x00001000
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#define USBSTS_RCL 0x00002000
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#define USBSTS_PERIODIC_SCHEDULE 0x00004000
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#define USBSTS_ASYNC_SCHEDULE 0x00008000
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/* Interrupt Enable Register Bit Masks */
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#define USBINTR_INT_EN (0x00000001)
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#define USBINTR_ERR_INT_EN (0x00000002)
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#define USBINTR_PORT_CHANGE_DETECT_EN (0x00000004)
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#define USBINTR_ASYNC_ADV_AAE (0x00000020)
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#define USBINTR_ASYNC_ADV_AAE_ENABLE (0x00000020)
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#define USBINTR_ASYNC_ADV_AAE_DISABLE (0xFFFFFFDF)
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#define USBINTR_RESET_EN (0x00000040)
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#define USBINTR_SOF_UFRAME_EN (0x00000080)
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#define USBINTR_DEVICE_SUSPEND (0x00000100)
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#define USB_DEVICE_ADDRESS_MASK (0xfe000000)
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#define USB_DEVICE_ADDRESS_BIT_SHIFT (25)
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struct mv_cap_regs {
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u32 caplength_hciversion;
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u32 hcsparams; /* HC structural parameters */
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u32 hccparams; /* HC Capability Parameters*/
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u32 reserved[5];
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u32 dciversion; /* DC version number and reserved 16 bits */
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u32 dccparams; /* DC Capability Parameters */
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};
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struct mv_op_regs {
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u32 usbcmd; /* Command register */
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u32 usbsts; /* Status register */
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u32 usbintr; /* Interrupt enable */
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u32 frindex; /* Frame index */
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u32 reserved1[1];
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u32 deviceaddr; /* Device Address */
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u32 eplistaddr; /* Endpoint List Address */
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u32 ttctrl; /* HOST TT status and control */
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u32 burstsize; /* Programmable Burst Size */
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u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
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u32 reserved[4];
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u32 epnak; /* Endpoint NAK */
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u32 epnaken; /* Endpoint NAK Enable */
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u32 configflag; /* Configured Flag register */
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u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
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u32 otgsc;
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u32 usbmode; /* USB Host/Device mode */
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u32 epsetupstat; /* Endpoint Setup Status */
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u32 epprime; /* Endpoint Initialize */
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u32 epflush; /* Endpoint De-initialize */
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u32 epstatus; /* Endpoint Status */
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u32 epcomplete; /* Endpoint Interrupt On Complete */
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u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
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u32 mcr; /* Mux Control */
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u32 isr; /* Interrupt Status */
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u32 ier; /* Interrupt Enable */
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};
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struct mv_udc {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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spinlock_t lock;
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struct completion *done;
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struct platform_device *dev;
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int irq;
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struct mv_cap_regs __iomem *cap_regs;
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struct mv_op_regs __iomem *op_regs;
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unsigned int phy_regs;
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unsigned int max_eps;
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struct mv_dqh *ep_dqh;
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size_t ep_dqh_size;
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dma_addr_t ep_dqh_dma;
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struct dma_pool *dtd_pool;
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struct mv_ep *eps;
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struct mv_dtd *dtd_head;
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struct mv_dtd *dtd_tail;
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unsigned int dtd_entries;
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struct mv_req *status_req;
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struct usb_ctrlrequest local_setup_buff;
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unsigned int resume_state; /* USB state to resume */
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unsigned int usb_state; /* USB current state */
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unsigned int ep0_state; /* Endpoint zero state */
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unsigned int ep0_dir;
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unsigned int dev_addr;
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int errors;
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unsigned softconnect:1,
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vbus_active:1,
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remote_wakeup:1,
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softconnected:1,
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force_fs:1;
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struct clk *clk;
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};
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/* endpoint data structure */
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struct mv_ep {
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struct usb_ep ep;
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struct mv_udc *udc;
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struct list_head queue;
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struct mv_dqh *dqh;
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const struct usb_endpoint_descriptor *desc;
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u32 direction;
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char name[14];
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unsigned stopped:1,
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wedge:1,
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ep_type:2,
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ep_num:8;
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};
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/* request data structure */
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struct mv_req {
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struct usb_request req;
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struct mv_dtd *dtd, *head, *tail;
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struct mv_ep *ep;
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struct list_head queue;
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unsigned dtd_count;
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unsigned mapped:1;
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};
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#define EP_QUEUE_HEAD_MULT_POS 30
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#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000
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#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16
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#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff)
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#define EP_QUEUE_HEAD_IOS 0x00008000
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#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001
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#define EP_QUEUE_HEAD_IOC 0x00008000
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#define EP_QUEUE_HEAD_MULTO 0x00000C00
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#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040
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#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080
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#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF
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#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0
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#define EP_QUEUE_FRINDEX_MASK 0x000007FF
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#define EP_MAX_LENGTH_TRANSFER 0x4000
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struct mv_dqh {
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/* Bits 16..26 Bit 15 is Interrupt On Setup */
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u32 max_packet_length;
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u32 curr_dtd_ptr; /* Current dTD Pointer */
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u32 next_dtd_ptr; /* Next dTD Pointer */
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/* Total bytes (16..30), IOC (15), INT (8), STS (0-7) */
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u32 size_ioc_int_sts;
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u32 buff_ptr0; /* Buffer pointer Page 0 (12-31) */
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u32 buff_ptr1; /* Buffer pointer Page 1 (12-31) */
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u32 buff_ptr2; /* Buffer pointer Page 2 (12-31) */
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u32 buff_ptr3; /* Buffer pointer Page 3 (12-31) */
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u32 buff_ptr4; /* Buffer pointer Page 4 (12-31) */
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u32 reserved1;
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/* 8 bytes of setup data that follows the Setup PID */
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u8 setup_buffer[8];
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u32 reserved2[4];
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};
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#define DTD_NEXT_TERMINATE (0x00000001)
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#define DTD_IOC (0x00008000)
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#define DTD_STATUS_ACTIVE (0x00000080)
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#define DTD_STATUS_HALTED (0x00000040)
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#define DTD_STATUS_DATA_BUFF_ERR (0x00000020)
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#define DTD_STATUS_TRANSACTION_ERR (0x00000008)
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#define DTD_RESERVED_FIELDS (0x00007F00)
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#define DTD_ERROR_MASK (0x68)
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#define DTD_ADDR_MASK (0xFFFFFFE0)
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#define DTD_PACKET_SIZE 0x7FFF0000
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#define DTD_LENGTH_BIT_POS (16)
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struct mv_dtd {
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u32 dtd_next;
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u32 size_ioc_sts;
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u32 buff_ptr0; /* Buffer pointer Page 0 */
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u32 buff_ptr1; /* Buffer pointer Page 1 */
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u32 buff_ptr2; /* Buffer pointer Page 2 */
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u32 buff_ptr3; /* Buffer pointer Page 3 */
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u32 buff_ptr4; /* Buffer pointer Page 4 */
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u32 scratch_ptr;
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/* 32 bytes */
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dma_addr_t td_dma; /* dma address for this td */
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struct mv_dtd *next_dtd_virt;
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};
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extern int mv_udc_phy_init(unsigned int base);
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#endif
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