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1e55b609b9
Use unified version of the copyright notice in the files Update copyright years according the year the files were touched, except this patch and SPDX conversions. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
240 lines
8.4 KiB
C
240 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (c) 2013-2014, Intel Corporation. All rights reserved.
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* Intel Management Engine Interface (Intel MEI) Linux driver
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*/
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#ifndef _MEI_HW_TXE_REGS_H_
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#define _MEI_HW_TXE_REGS_H_
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#include "hw.h"
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#define SEC_ALIVENESS_TIMER_TIMEOUT (5 * MSEC_PER_SEC)
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#define SEC_ALIVENESS_WAIT_TIMEOUT (1 * MSEC_PER_SEC)
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#define SEC_RESET_WAIT_TIMEOUT (1 * MSEC_PER_SEC)
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#define SEC_READY_WAIT_TIMEOUT (5 * MSEC_PER_SEC)
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#define START_MESSAGE_RESPONSE_WAIT_TIMEOUT (5 * MSEC_PER_SEC)
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#define RESET_CANCEL_WAIT_TIMEOUT (1 * MSEC_PER_SEC)
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enum {
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SEC_BAR,
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BRIDGE_BAR,
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NUM_OF_MEM_BARS
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};
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/* SeC FW Status Register
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*
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* FW uses this register in order to report its status to host.
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* This register resides in PCI-E config space.
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*/
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#define PCI_CFG_TXE_FW_STS0 0x40
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# define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK 0x0000000F
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# define PCI_CFG_TXE_FW_STS0_OP_ST_MSK 0x000001C0
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# define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
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# define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK 0x0000F000
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# define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK 0x000F0000
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# define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK 0x00F00000
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#define PCI_CFG_TXE_FW_STS1 0x48
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#define IPC_BASE_ADDR 0x80400 /* SeC IPC Base Address */
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/* IPC Input Doorbell Register */
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#define SEC_IPC_INPUT_DOORBELL_REG (0x0000 + IPC_BASE_ADDR)
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/* IPC Input Status Register
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* This register indicates whether or not processing of
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* the most recent command has been completed by the SEC
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* New commands and payloads should not be written by the Host
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* until this indicates that the previous command has been processed.
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*/
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#define SEC_IPC_INPUT_STATUS_REG (0x0008 + IPC_BASE_ADDR)
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# define SEC_IPC_INPUT_STATUS_RDY BIT(0)
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/* IPC Host Interrupt Status Register */
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#define SEC_IPC_HOST_INT_STATUS_REG (0x0010 + IPC_BASE_ADDR)
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#define SEC_IPC_HOST_INT_STATUS_OUT_DB BIT(0)
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#define SEC_IPC_HOST_INT_STATUS_IN_RDY BIT(1)
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#define SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD BIT(5)
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#define SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS BIT(17)
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#define SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR BIT(18)
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#define SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR BIT(19)
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#define SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW BIT(21)
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/* Convenient mask for pending interrupts */
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#define SEC_IPC_HOST_INT_STATUS_PENDING \
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(SEC_IPC_HOST_INT_STATUS_OUT_DB| \
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SEC_IPC_HOST_INT_STATUS_IN_RDY)
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/* IPC Host Interrupt Mask Register */
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#define SEC_IPC_HOST_INT_MASK_REG (0x0014 + IPC_BASE_ADDR)
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# define SEC_IPC_HOST_INT_MASK_OUT_DB BIT(0) /* Output Doorbell Int Mask */
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# define SEC_IPC_HOST_INT_MASK_IN_RDY BIT(1) /* Input Ready Int Mask */
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/* IPC Input Payload RAM */
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#define SEC_IPC_INPUT_PAYLOAD_REG (0x0100 + IPC_BASE_ADDR)
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/* IPC Shared Payload RAM */
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#define IPC_SHARED_PAYLOAD_REG (0x0200 + IPC_BASE_ADDR)
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/* SeC Address Translation Table Entry 2 - Ctrl
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*
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* This register resides also in SeC's PCI-E Memory space.
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*/
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#define SATT2_CTRL_REG 0x1040
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# define SATT2_CTRL_VALID_MSK BIT(0)
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# define SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT 8
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# define SATT2_CTRL_BRIDGE_HOST_EN_MSK BIT(12)
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/* SATT Table Entry 2 SAP Base Address Register */
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#define SATT2_SAP_BA_REG 0x1044
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/* SATT Table Entry 2 SAP Size Register. */
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#define SATT2_SAP_SIZE_REG 0x1048
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/* SATT Table Entry 2 SAP Bridge Address - LSB Register */
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#define SATT2_BRG_BA_LSB_REG 0x104C
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/* Host High-level Interrupt Status Register */
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#define HHISR_REG 0x2020
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/* Host High-level Interrupt Enable Register
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*
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* Resides in PCI memory space. This is the top hierarchy for
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* interrupts from SeC to host, aggregating both interrupts that
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* arrive through HICR registers as well as interrupts
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* that arrive via IPC.
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*/
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#define HHIER_REG 0x2024
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#define IPC_HHIER_SEC BIT(0)
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#define IPC_HHIER_BRIDGE BIT(1)
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#define IPC_HHIER_MSK (IPC_HHIER_SEC | IPC_HHIER_BRIDGE)
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/* Host High-level Interrupt Mask Register.
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*
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* Resides in PCI memory space.
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* This is the top hierarchy for masking interrupts from SeC to host.
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*/
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#define HHIMR_REG 0x2028
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#define IPC_HHIMR_SEC BIT(0)
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#define IPC_HHIMR_BRIDGE BIT(1)
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/* Host High-level IRQ Status Register */
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#define HHIRQSR_REG 0x202C
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/* Host Interrupt Cause Register 0 - SeC IPC Readiness
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*
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* This register is both an ICR to Host from PCI Memory Space
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* and it is also exposed in the SeC memory space.
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* This register is used by SeC's IPC driver in order
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* to synchronize with host about IPC interface state.
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*/
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#define HICR_SEC_IPC_READINESS_REG 0x2040
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#define HICR_SEC_IPC_READINESS_HOST_RDY BIT(0)
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#define HICR_SEC_IPC_READINESS_SEC_RDY BIT(1)
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#define HICR_SEC_IPC_READINESS_SYS_RDY \
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(HICR_SEC_IPC_READINESS_HOST_RDY | \
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HICR_SEC_IPC_READINESS_SEC_RDY)
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#define HICR_SEC_IPC_READINESS_RDY_CLR BIT(2)
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/* Host Interrupt Cause Register 1 - Aliveness Response */
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/* This register is both an ICR to Host from PCI Memory Space
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* and it is also exposed in the SeC memory space.
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* The register may be used by SeC to ACK a host request for aliveness.
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*/
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#define HICR_HOST_ALIVENESS_RESP_REG 0x2044
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#define HICR_HOST_ALIVENESS_RESP_ACK BIT(0)
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/* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */
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#define HICR_SEC_IPC_OUTPUT_DOORBELL_REG 0x2048
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/* Host Interrupt Status Register.
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*
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* Resides in PCI memory space.
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* This is the main register involved in generating interrupts
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* from SeC to host via HICRs.
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* The interrupt generation rules are as follows:
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* An interrupt will be generated whenever for any i,
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* there is a transition from a state where at least one of
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* the following conditions did not hold, to a state where
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* ALL the following conditions hold:
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* A) HISR.INT[i]_STS == 1.
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* B) HIER.INT[i]_EN == 1.
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*/
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#define HISR_REG 0x2060
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#define HISR_INT_0_STS BIT(0)
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#define HISR_INT_1_STS BIT(1)
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#define HISR_INT_2_STS BIT(2)
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#define HISR_INT_3_STS BIT(3)
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#define HISR_INT_4_STS BIT(4)
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#define HISR_INT_5_STS BIT(5)
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#define HISR_INT_6_STS BIT(6)
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#define HISR_INT_7_STS BIT(7)
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#define HISR_INT_STS_MSK \
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(HISR_INT_0_STS | HISR_INT_1_STS | HISR_INT_2_STS)
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/* Host Interrupt Enable Register. Resides in PCI memory space. */
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#define HIER_REG 0x2064
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#define HIER_INT_0_EN BIT(0)
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#define HIER_INT_1_EN BIT(1)
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#define HIER_INT_2_EN BIT(2)
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#define HIER_INT_3_EN BIT(3)
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#define HIER_INT_4_EN BIT(4)
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#define HIER_INT_5_EN BIT(5)
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#define HIER_INT_6_EN BIT(6)
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#define HIER_INT_7_EN BIT(7)
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#define HIER_INT_EN_MSK \
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(HIER_INT_0_EN | HIER_INT_1_EN | HIER_INT_2_EN)
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/* SEC Memory Space IPC output payload.
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*
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* This register is part of the output payload which SEC provides to host.
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*/
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#define BRIDGE_IPC_OUTPUT_PAYLOAD_REG 0x20C0
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/* SeC Interrupt Cause Register - Host Aliveness Request
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* This register is both an ICR to SeC and it is also exposed
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* in the host-visible PCI memory space.
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* The register is used by host to request SeC aliveness.
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*/
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#define SICR_HOST_ALIVENESS_REQ_REG 0x214C
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#define SICR_HOST_ALIVENESS_REQ_REQUESTED BIT(0)
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/* SeC Interrupt Cause Register - Host IPC Readiness
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*
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* This register is both an ICR to SeC and it is also exposed
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* in the host-visible PCI memory space.
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* This register is used by the host's SeC driver uses in order
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* to synchronize with SeC about IPC interface state.
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*/
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#define SICR_HOST_IPC_READINESS_REQ_REG 0x2150
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#define SICR_HOST_IPC_READINESS_HOST_RDY BIT(0)
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#define SICR_HOST_IPC_READINESS_SEC_RDY BIT(1)
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#define SICR_HOST_IPC_READINESS_SYS_RDY \
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(SICR_HOST_IPC_READINESS_HOST_RDY | \
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SICR_HOST_IPC_READINESS_SEC_RDY)
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#define SICR_HOST_IPC_READINESS_RDY_CLR BIT(2)
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/* SeC Interrupt Cause Register - SeC IPC Output Status
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*
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* This register indicates whether or not processing of the most recent
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* command has been completed by the Host.
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* New commands and payloads should not be written by SeC until this
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* register indicates that the previous command has been processed.
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*/
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#define SICR_SEC_IPC_OUTPUT_STATUS_REG 0x2154
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# define SEC_IPC_OUTPUT_STATUS_RDY BIT(0)
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/* MEI IPC Message payload size 64 bytes */
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#define PAYLOAD_SIZE 64
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/* MAX size for SATT range 32MB */
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#define SATT_RANGE_MAX (32 << 20)
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#endif /* _MEI_HW_TXE_REGS_H_ */
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