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1b5bda21b0
Documentation for APM X-Gene SoC GPIO controller DTS binding. Signed-off-by: Feng Kan <fkan@apm.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
23 lines
664 B
Plaintext
23 lines
664 B
Plaintext
APM X-Gene SoC GPIO controller bindings
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This is a gpio controller that is part of the flash controller.
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This gpio controller controls a total of 48 gpios.
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Required properties:
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- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
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- reg: Physical base address and size of the controller's registers
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- #gpio-cells: Should be two.
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- first cell is the pin number
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- second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- gpio-controller: Marks the device node as a GPIO controller.
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Example:
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gpio0: gpio0@1701c000 {
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compatible = "apm,xgene-gpio";
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reg = <0x0 0x1701c000 0x0 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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