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https://github.com/edk2-porting/linux-next.git
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faff3d8e85
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
189 lines
4.9 KiB
Plaintext
189 lines
4.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CLK_RENESAS
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bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
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default y if ARCH_RENESAS
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select CLK_EMEV2 if ARCH_EMEV2
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select CLK_RZA1 if ARCH_R7S72100
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select CLK_R7S9210 if ARCH_R7S9210
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select CLK_R8A73A4 if ARCH_R8A73A4
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select CLK_R8A7740 if ARCH_R8A7740
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select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
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select CLK_R8A7745 if ARCH_R8A7745
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select CLK_R8A77470 if ARCH_R8A77470
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select CLK_R8A774A1 if ARCH_R8A774A1
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select CLK_R8A774C0 if ARCH_R8A774C0
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select CLK_R8A7778 if ARCH_R8A7778
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select CLK_R8A7779 if ARCH_R8A7779
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select CLK_R8A7790 if ARCH_R8A7790
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select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
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select CLK_R8A7792 if ARCH_R8A7792
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select CLK_R8A7794 if ARCH_R8A7794
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select CLK_R8A7795 if ARCH_R8A7795
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select CLK_R8A7796 if ARCH_R8A7796
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select CLK_R8A77965 if ARCH_R8A77965
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select CLK_R8A77970 if ARCH_R8A77970
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select CLK_R8A77980 if ARCH_R8A77980
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select CLK_R8A77990 if ARCH_R8A77990
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select CLK_R8A77995 if ARCH_R8A77995
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select CLK_R9A06G032 if ARCH_R9A06G032
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select CLK_SH73A0 if ARCH_SH73A0
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if CLK_RENESAS
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config CLK_RENESAS_LEGACY
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bool "Legacy DT clock support"
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depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
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help
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Enable backward compatibility with old device trees describing a
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hierarchical representation of the various CPG and MSTP clocks.
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Say Y if you want your kernel to work with old DTBs.
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It is safe to say N if you use the DTS that is supplied with the
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current kernel source tree.
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# SoC
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config CLK_EMEV2
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bool "Emma Mobile EV2 clock support" if COMPILE_TEST
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config CLK_RZA1
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bool "RZ/A1H clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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config CLK_R7S9210
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bool "RZ/A2 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_R8A73A4
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bool "R-Mobile APE6 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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select CLK_RENESAS_DIV6
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config CLK_R8A7740
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bool "R-Mobile A1 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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select CLK_RENESAS_DIV6
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config CLK_R8A7743
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bool "RZ/G1M clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A7745
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bool "RZ/G1E clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A77470
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bool "RZ/G1C clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A774A1
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bool "RZ/G2M clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A774C0
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bool "RZ/G2E clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A7778
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bool "R-Car M1A clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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config CLK_R8A7779
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bool "R-Car H1 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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config CLK_R8A7790
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bool "R-Car H2 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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select CLK_RENESAS_DIV6
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config CLK_R8A7791
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bool "R-Car M2-W/N clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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select CLK_RENESAS_DIV6
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config CLK_R8A7792
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bool "R-Car V2H clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A7794
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bool "R-Car E2 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
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select CLK_RCAR_GEN2_CPG
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select CLK_RENESAS_DIV6
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config CLK_R8A7795
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bool "R-Car H3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A7796
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bool "R-Car M3-W clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77965
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bool "R-Car M3-N clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77970
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bool "R-Car V3M clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77980
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bool "R-Car V3H clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77990
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bool "R-Car E3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A77995
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bool "R-Car D3 clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R9A06G032
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bool "Renesas R9A06G032 clock driver"
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help
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This is a driver for R9A06G032 clocks
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config CLK_SH73A0
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bool "SH-Mobile AG5 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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select CLK_RENESAS_DIV6
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# Family
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config CLK_RCAR_GEN2
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bool "R-Car Gen2 legacy clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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select CLK_RENESAS_DIV6
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config CLK_RCAR_GEN2_CPG
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bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_RCAR_GEN3_CPG
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bool "R-Car Gen3 CPG clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_RCAR_USB2_CLOCK_SEL
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bool "Renesas R-Car USB2 clock selector support"
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depends on ARCH_RENESAS || COMPILE_TEST
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help
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This is a driver for R-Car USB2 clock selector
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# Generic
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config CLK_RENESAS_CPG_MSSR
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bool "CPG/MSSR clock support" if COMPILE_TEST
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select CLK_RENESAS_DIV6
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config CLK_RENESAS_CPG_MSTP
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bool "MSTP clock support" if COMPILE_TEST
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config CLK_RENESAS_DIV6
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bool "DIV6 clock support" if COMPILE_TEST
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endif # CLK_RENESAS
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