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https://github.com/edk2-porting/linux-next.git
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c5f48c0a7a
Go over the IRQ subsystem source code (including irqchip drivers) and fix common typos in comments. No change in functionality intended. Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: linux-kernel@vger.kernel.org
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* H8S interrupt controller driver
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*
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* Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/io.h>
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static void *intc_baseaddr;
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#define IPRA (intc_baseaddr)
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static const unsigned char ipr_table[] = {
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0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */
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0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */
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0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */
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0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */
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0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */
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0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */
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0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */
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0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */
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0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */
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0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */
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0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */
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0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */
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0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */
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0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */
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};
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static void h8s_disable_irq(struct irq_data *data)
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{
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int pos;
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void __iomem *addr;
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unsigned short pri;
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int irq = data->irq;
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addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
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pos = (ipr_table[irq - 16] & 0x0f) * 4;
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pri = ~(0x000f << pos);
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pri &= readw(addr);
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writew(pri, addr);
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}
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static void h8s_enable_irq(struct irq_data *data)
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{
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int pos;
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void __iomem *addr;
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unsigned short pri;
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int irq = data->irq;
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addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
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pos = (ipr_table[irq - 16] & 0x0f) * 4;
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pri = ~(0x000f << pos);
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pri &= readw(addr);
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pri |= 1 << pos;
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writew(pri, addr);
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}
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struct irq_chip h8s_irq_chip = {
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.name = "H8S-INTC",
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.irq_enable = h8s_enable_irq,
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.irq_disable = h8s_disable_irq,
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};
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static __init int irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw_irq_num)
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{
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irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq);
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return 0;
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}
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static const struct irq_domain_ops irq_ops = {
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.map = irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init h8s_intc_of_init(struct device_node *intc,
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struct device_node *parent)
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{
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struct irq_domain *domain;
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int n;
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intc_baseaddr = of_iomap(intc, 0);
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BUG_ON(!intc_baseaddr);
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/* All interrupt priority is 0 (disable) */
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/* IPRA to IPRK */
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for (n = 0; n <= 'k' - 'a'; n++)
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writew(0x0000, IPRA + (n * 2));
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domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
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BUG_ON(!domain);
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irq_set_default_host(domain);
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return 0;
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}
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IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init);
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