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2bf3016f89
This patch enables 32bit PPC's (with 36bit physical address space, e.g. IBM/AMCC PPC44x) to run with >= 4GB of RAM. Mostly its just replacing types (unsigned long -> phys_addr_t). Tested on an AMCC Katmai with 4GB of DDR2. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
/*
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* Declarations of procedures and variables shared between files
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* in arch/ppc/mm/.
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/mm.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu.h>
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extern void hash_preload(struct mm_struct *mm, unsigned long ea,
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unsigned long access, unsigned long trap);
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#ifdef CONFIG_PPC32
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extern void mapin_ram(void);
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extern int map_page(unsigned long va, phys_addr_t pa, int flags);
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extern void setbat(int index, unsigned long virt, phys_addr_t phys,
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unsigned int size, int flags);
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extern void settlbcam(int index, unsigned long virt, phys_addr_t phys,
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unsigned int size, int flags, unsigned int pid);
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extern void invalidate_tlbcam_entry(int index);
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extern int __map_without_bats;
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extern unsigned long ioremap_base;
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extern unsigned int rtas_data, rtas_size;
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struct hash_pte;
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extern struct hash_pte *Hash, *Hash_end;
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extern unsigned long Hash_size, Hash_mask;
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extern unsigned int num_tlbcam_entries;
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#endif
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extern unsigned long ioremap_bot;
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extern unsigned long __max_low_memory;
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extern phys_addr_t __initial_memory_limit_addr;
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extern phys_addr_t total_memory;
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extern phys_addr_t total_lowmem;
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extern phys_addr_t memstart_addr;
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extern phys_addr_t lowmem_end_addr;
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/* ...and now those things that may be slightly different between processor
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* architectures. -- Dan
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*/
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#if defined(CONFIG_8xx)
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#define flush_HPTE(X, va, pg) _tlbie(va, 0 /* 8xx doesn't care about PID */)
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#define MMU_init_hw() do { } while(0)
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#define mmu_mapin_ram() (0UL)
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#elif defined(CONFIG_4xx)
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#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
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extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(void);
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#elif defined(CONFIG_FSL_BOOKE)
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#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
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extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(void);
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extern void adjust_total_lowmem(void);
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#elif defined(CONFIG_PPC32)
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/* anything 32-bit except 4xx or 8xx */
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extern void MMU_init_hw(void);
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extern unsigned long mmu_mapin_ram(void);
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/* Be careful....this needs to be updated if we ever encounter 603 SMPs,
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* which includes all new 82xx processors. We need tlbie/tlbsync here
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* in that case (I think). -- Dan.
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*/
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static inline void flush_HPTE(unsigned context, unsigned long va,
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unsigned long pdval)
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{
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if ((Hash != 0) &&
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cpu_has_feature(CPU_FTR_HPTE_TABLE))
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flush_hash_pages(0, va, pdval, 1);
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else
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_tlbie(va);
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}
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#endif
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