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2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
222 lines
5.6 KiB
C
222 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2004 ICT CAS
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* Author: Li xiaoyu, ICT CAS
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* lixy@ict.ac.cn
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*
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* Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <loongson.h>
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/* South bridge slot number is set by the pci probe process */
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static u8 sb_slot = 5;
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = 0;
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if (slot == sb_slot) {
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switch (PCI_FUNC(dev->devfn)) {
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case 2:
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irq = 10;
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break;
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case 3:
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irq = 11;
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break;
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case 5:
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irq = 9;
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break;
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}
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} else {
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irq = LOONGSON_IRQ_BASE + 25 + pin;
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}
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return irq;
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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static void loongson2e_nec_fixup(struct pci_dev *pdev)
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{
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unsigned int val;
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/* Configures port 1, 2, 3, 4 to be validate*/
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pci_read_config_dword(pdev, 0xe0, &val);
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pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4);
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/* System clock is 48-MHz Oscillator. */
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pci_write_config_dword(pdev, 0xe4, 1 << 5);
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}
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static void loongson2e_686b_func0_fixup(struct pci_dev *pdev)
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{
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unsigned char c;
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sb_slot = PCI_SLOT(pdev->devfn);
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printk(KERN_INFO "via686b fix: ISA bridge\n");
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/* Enable I/O Recovery time */
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pci_write_config_byte(pdev, 0x40, 0x08);
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/* Enable ISA refresh */
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pci_write_config_byte(pdev, 0x41, 0x01);
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/* disable ISA line buffer */
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pci_write_config_byte(pdev, 0x45, 0x00);
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/* Gate INTR, and flush line buffer */
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pci_write_config_byte(pdev, 0x46, 0xe0);
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/* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */
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/* pci_write_config_byte(pdev, 0x47, 0x20); */
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/*
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* enable PCI Delay Transaction, Enable EISA ports 4D0/4D1.
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* enable time-out timer
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*/
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pci_write_config_byte(pdev, 0x47, 0xe6);
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/*
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* enable level trigger on pci irqs: 9,10,11,13
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* important! without this PCI interrupts won't work
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*/
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outb(0x2e, 0x4d1);
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/* 512 K PCI Decode */
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pci_write_config_byte(pdev, 0x48, 0x01);
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/* Wait for PGNT before grant to ISA Master/DMA */
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pci_write_config_byte(pdev, 0x4a, 0x84);
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/*
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* Plug'n'Play
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*
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* Parallel DRQ 3, Floppy DRQ 2 (default)
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*/
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pci_write_config_byte(pdev, 0x50, 0x0e);
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/*
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* IRQ Routing for Floppy and Parallel port
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*
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* IRQ 6 for floppy, IRQ 7 for parallel port
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*/
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pci_write_config_byte(pdev, 0x51, 0x76);
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/* IRQ Routing for serial ports (take IRQ 3 and 4) */
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pci_write_config_byte(pdev, 0x52, 0x34);
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/* All IRQ's level triggered. */
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pci_write_config_byte(pdev, 0x54, 0x00);
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/* route PIRQA-D irq */
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pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */
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pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */
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/* 3-0, PIRQB */
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pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */
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/* enable function 5/6, audio/modem */
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pci_read_config_byte(pdev, 0x85, &c);
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c &= ~(0x3 << 2);
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pci_write_config_byte(pdev, 0x85, c);
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printk(KERN_INFO"via686b fix: ISA bridge done\n");
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}
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static void loongson2e_686b_func1_fixup(struct pci_dev *pdev)
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{
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printk(KERN_INFO"via686b fix: IDE\n");
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/* Modify IDE controller setup */
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48);
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pci_write_config_byte(pdev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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pci_write_config_byte(pdev, 0x40, 0x0b);
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/* legacy mode */
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pci_write_config_byte(pdev, 0x42, 0x09);
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#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */
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/* disable read prefetch/write post buffers */
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pci_write_config_byte(pdev, 0x41, 0x02);
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/* use 3/4 as fifo thresh hold */
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pci_write_config_byte(pdev, 0x43, 0x0a);
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pci_write_config_byte(pdev, 0x44, 0x00);
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pci_write_config_byte(pdev, 0x45, 0x00);
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#else
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pci_write_config_byte(pdev, 0x41, 0xc2);
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pci_write_config_byte(pdev, 0x43, 0x35);
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pci_write_config_byte(pdev, 0x44, 0x1c);
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pci_write_config_byte(pdev, 0x45, 0x10);
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#endif
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printk(KERN_INFO"via686b fix: IDE done\n");
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}
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static void loongson2e_686b_func2_fixup(struct pci_dev *pdev)
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{
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/* irq routing */
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pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
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}
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static void loongson2e_686b_func3_fixup(struct pci_dev *pdev)
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{
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/* irq routing */
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pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
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}
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static void loongson2e_686b_func5_fixup(struct pci_dev *pdev)
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{
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unsigned int val;
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unsigned char c;
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/* enable IO */
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pci_write_config_byte(pdev, PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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pci_read_config_dword(pdev, 0x4, &val);
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pci_write_config_dword(pdev, 0x4, val | 1);
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/* route ac97 IRQ */
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pci_write_config_byte(pdev, 0x3c, 9);
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pci_read_config_byte(pdev, 0x8, &c);
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/* link control: enable link & SGD PCM output */
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pci_write_config_byte(pdev, 0x41, 0xcc);
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/* disable game port, FM, midi, sb, enable write to reg2c-2f */
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pci_write_config_byte(pdev, 0x42, 0x20);
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/* we are using Avance logic codec */
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pci_write_config_word(pdev, 0x2c, 0x1005);
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pci_write_config_word(pdev, 0x2e, 0x4710);
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pci_read_config_dword(pdev, 0x2c, &val);
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pci_write_config_byte(pdev, 0x42, 0x0);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
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loongson2e_686b_func0_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
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loongson2e_686b_func1_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2,
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loongson2e_686b_func2_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3,
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loongson2e_686b_func3_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5,
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loongson2e_686b_func5_fixup);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
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loongson2e_nec_fixup);
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