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9ee417c074
some of anatop's regulators(cpu, vddpu and vddsoc) have register settings about LDO's step time, which will impact the LDO ramp up speed, need to use set_voltage_time_sel interface to add necessary delay everytime LDOs' voltage is increased. offset 0x170: bit [24-25]: cpu bit [26-27]: vddpu bit [28-29]: vddsoc field definition: 0'b00: 64 cycles of 24M clock; 0'b01: 128 cycles of 24M clock; 0'b02: 256 cycles of 24M clock; 0'b03: 512 cycles of 24M clock; Signed-off-by: Anson Huang <b20788@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
Anatop Voltage regulators
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Required properties:
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- compatible: Must be "fsl,anatop-regulator"
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- anatop-reg-offset: Anatop MFD register offset
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- anatop-vol-bit-shift: Bit shift for the register
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- anatop-vol-bit-width: Number of bits used in the register
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- anatop-min-bit-val: Minimum value of this register
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- anatop-min-voltage: Minimum voltage of this regulator
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- anatop-max-voltage: Maximum voltage of this regulator
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Optional properties:
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- anatop-delay-reg-offset: Anatop MFD step time register offset
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- anatop-delay-bit-shift: Bit shift for the step time register
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- anatop-delay-bit-width: Number of bits used in the step time register
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Any property defined as part of the core regulator
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binding, defined in regulator.txt, can also be used.
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Example:
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regulator-vddpu {
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compatible = "fsl,anatop-regulator";
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regulator-name = "vddpu";
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regulator-min-microvolt = <725000>;
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regulator-max-microvolt = <1300000>;
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regulator-always-on;
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anatop-reg-offset = <0x140>;
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anatop-vol-bit-shift = <9>;
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anatop-vol-bit-width = <5>;
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anatop-delay-reg-offset = <0x170>;
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anatop-delay-bit-shift = <24>;
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anatop-delay-bit-width = <2>;
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anatop-min-bit-val = <1>;
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anatop-min-voltage = <725000>;
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anatop-max-voltage = <1300000>;
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};
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