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2ed71e7531
This patch removes the use of the IRQF_DISABLED flag from arch/arm/mach-w90x900/time.c It's a NOOP since 2.6.35 and it will be removed one day. Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com> Acked-by: Wan zongshun <mcuos.com@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
169 lines
3.7 KiB
C
169 lines
3.7 KiB
C
/*
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* linux/arch/arm/mach-w90x900/time.c
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*
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* Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
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*
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* Copyright (c) 2009 Nuvoton technology corporation
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* All rights reserved.
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*
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* Wan ZongShun <mcuos.com@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/leds.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/mach-types.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <mach/map.h>
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#include <mach/regs-timer.h>
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#include "nuc9xx.h"
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#define RESETINT 0x1f
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#define PERIOD (0x01 << 27)
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#define ONESHOT (0x00 << 27)
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#define COUNTEN (0x01 << 30)
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#define INTEN (0x01 << 29)
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#define TICKS_PER_SEC 100
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#define PRESCALE 0x63 /* Divider = prescale + 1 */
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#define TDR_SHIFT 24
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static unsigned int timer0_load;
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static void nuc900_clockevent_setmode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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unsigned int val;
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val = __raw_readl(REG_TCSR0);
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val &= ~(0x03 << 27);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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__raw_writel(timer0_load, REG_TICR0);
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val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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__raw_writel(val, REG_TCSR0);
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}
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static int nuc900_clockevent_setnextevent(unsigned long evt,
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struct clock_event_device *clk)
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{
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unsigned int val;
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__raw_writel(evt, REG_TICR0);
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val = __raw_readl(REG_TCSR0);
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val |= (COUNTEN | INTEN | PRESCALE);
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__raw_writel(val, REG_TCSR0);
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return 0;
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}
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static struct clock_event_device nuc900_clockevent_device = {
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.name = "nuc900-timer0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = nuc900_clockevent_setmode,
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.set_next_event = nuc900_clockevent_setnextevent,
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.rating = 300,
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};
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/*IRQ handler for the timer*/
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static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &nuc900_clockevent_device;
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__raw_writel(0x01, REG_TISR); /* clear TIF0 */
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction nuc900_timer0_irq = {
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.name = "nuc900-timer0",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = nuc900_timer0_interrupt,
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};
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static void __init nuc900_clockevents_init(void)
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{
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unsigned int rate;
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struct clk *clk = clk_get(NULL, "timer0");
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BUG_ON(IS_ERR(clk));
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__raw_writel(0x00, REG_TCSR0);
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clk_enable(clk);
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rate = clk_get_rate(clk) / (PRESCALE + 1);
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timer0_load = (rate / TICKS_PER_SEC);
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__raw_writel(RESETINT, REG_TISR);
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setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
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nuc900_clockevent_device.cpumask = cpumask_of(0);
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clockevents_config_and_register(&nuc900_clockevent_device, rate,
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0xf, 0xffffffff);
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}
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static void __init nuc900_clocksource_init(void)
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{
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unsigned int val;
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unsigned int rate;
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struct clk *clk = clk_get(NULL, "timer1");
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BUG_ON(IS_ERR(clk));
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__raw_writel(0x00, REG_TCSR1);
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clk_enable(clk);
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rate = clk_get_rate(clk) / (PRESCALE + 1);
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__raw_writel(0xffffffff, REG_TICR1);
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val = __raw_readl(REG_TCSR1);
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val |= (COUNTEN | PERIOD | PRESCALE);
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__raw_writel(val, REG_TCSR1);
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clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200,
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TDR_SHIFT, clocksource_mmio_readl_down);
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}
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void __init nuc900_timer_init(void)
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{
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nuc900_clocksource_init();
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nuc900_clockevents_init();
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}
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