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4796417417
Driver for Dave DNET ethernet controller found on Dave/DENX QongEVB-LITE FPGA. Heavily based on Dave sources, I've just adopted it to current kernel version and done some code cleanup. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: David S. Miller <davem@davemloft.net>
226 lines
7.1 KiB
C
226 lines
7.1 KiB
C
/*
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* Dave DNET Ethernet Controller driver
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*
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* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _DNET_H
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#define _DNET_H
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#define DRV_NAME "dnet"
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#define DRV_VERSION "0.9.1"
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#define PFX DRV_NAME ": "
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/* Register access macros */
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#define dnet_writel(port, value, reg) \
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writel((value), (port)->regs + DNET_##reg)
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#define dnet_readl(port, reg) readl((port)->regs + DNET_##reg)
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/* ALL DNET FIFO REGISTERS */
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#define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */
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#define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */
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#define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */
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#define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */
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/* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */
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#define DNET_VERCAPS 0x100 /* VERCAPS */
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#define DNET_INTR_SRC 0x104 /* INTR_SRC */
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#define DNET_INTR_ENB 0x108 /* INTR_ENB */
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#define DNET_RX_STATUS 0x10C /* RX_STATUS */
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#define DNET_TX_STATUS 0x110 /* TX_STATUS */
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#define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */
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#define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */
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#define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */
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#define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */
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#define DNET_SYS_CTL 0x124 /* SYS_CTL */
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#define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */
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#define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */
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#define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */
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/* ALL DNET MAC REGISTERS */
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#define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */
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#define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */
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/* ALL DNET RX STATISTICS COUNTERS */
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#define DNET_RX_PKT_IGNR_CNT 0x300
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#define DNET_RX_LEN_CHK_ERR_CNT 0x304
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#define DNET_RX_LNG_FRM_CNT 0x308
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#define DNET_RX_SHRT_FRM_CNT 0x30C
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#define DNET_RX_IPG_VIOL_CNT 0x310
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#define DNET_RX_CRC_ERR_CNT 0x314
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#define DNET_RX_OK_PKT_CNT 0x318
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#define DNET_RX_CTL_FRM_CNT 0x31C
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#define DNET_RX_PAUSE_FRM_CNT 0x320
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#define DNET_RX_MULTICAST_CNT 0x324
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#define DNET_RX_BROADCAST_CNT 0x328
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#define DNET_RX_VLAN_TAG_CNT 0x32C
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#define DNET_RX_PRE_SHRINK_CNT 0x330
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#define DNET_RX_DRIB_NIB_CNT 0x334
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#define DNET_RX_UNSUP_OPCD_CNT 0x338
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#define DNET_RX_BYTE_CNT 0x33C
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/* DNET TX STATISTICS COUNTERS */
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#define DNET_TX_UNICAST_CNT 0x400
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#define DNET_TX_PAUSE_FRM_CNT 0x404
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#define DNET_TX_MULTICAST_CNT 0x408
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#define DNET_TX_BRDCAST_CNT 0x40C
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#define DNET_TX_VLAN_TAG_CNT 0x410
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#define DNET_TX_BAD_FCS_CNT 0x414
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#define DNET_TX_JUMBO_CNT 0x418
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#define DNET_TX_BYTE_CNT 0x41C
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/* SOME INTERNAL MAC-CORE REGISTER */
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#define DNET_INTERNAL_MODE_REG 0x0
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#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
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#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
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#define DNET_INTERNAL_IGP_REG 0x8
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#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
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#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
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#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
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#define DNET_INTERNAL_TX_RX_STS_REG 0x12
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#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
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#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
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#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
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#define DNET_INTERNAL_WRITE (1 << 31)
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/* MAC-CORE REGISTER FIELDS */
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/* MAC-CORE MODE REGISTER FIELDS */
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#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
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#define DNET_INTERNAL_MODE_FCEN (1 << 1)
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#define DNET_INTERNAL_MODE_RXEN (1 << 2)
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#define DNET_INTERNAL_MODE_TXEN (1 << 3)
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/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
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#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
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#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
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#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
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#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
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#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
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#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
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#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
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#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
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#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
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/* SYSTEM CONTROL REGISTER FIELDS */
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#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
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#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
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#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
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#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
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/* TX STATUS REGISTER FIELDS */
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#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
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#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
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/* INTERRUPT SOURCE REGISTER FIELDS */
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#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
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#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
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#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
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#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
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#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
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#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
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#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
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#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
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#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
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#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
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#define DNET_INTR_SRC_PHY (1 << 19)
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/* INTERRUPT ENABLE REGISTER FIELDS */
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#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
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#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
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#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
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#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
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#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
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#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
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#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
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#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
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#define DNET_INTR_ENB_RX_ERROR (1 << 11)
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#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
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#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
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#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
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#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
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#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
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/* default values:
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* almost empty = less than one full sized ethernet frame (no jumbo) inside
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* the fifo almost full = can write less than one full sized ethernet frame
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* (no jumbo) inside the fifo
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*/
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#define DNET_CFG_TX_FIFO_FULL_THRES 25
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#define DNET_CFG_RX_FIFO_FULL_THRES 20
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/*
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* Capabilities. Used by the driver to know the capabilities that the ethernet
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* controller inside the FPGA have.
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*/
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#define DNET_HAS_MDIO (1 << 0)
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#define DNET_HAS_IRQ (1 << 1)
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#define DNET_HAS_GIGABIT (1 << 2)
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#define DNET_HAS_DMA (1 << 3)
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#define DNET_HAS_MII (1 << 4) /* or GMII */
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#define DNET_HAS_RMII (1 << 5) /* or RGMII */
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#define DNET_CAPS_MASK 0xFFFF
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#define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */
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#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
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#define DNET_FIFO_TX_DATA_AE_TH 384
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#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
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/*
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* Hardware-collected statistics.
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*/
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struct dnet_stats {
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u32 rx_pkt_ignr;
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u32 rx_len_chk_err;
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u32 rx_lng_frm;
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u32 rx_shrt_frm;
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u32 rx_ipg_viol;
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u32 rx_crc_err;
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u32 rx_ok_pkt;
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u32 rx_ctl_frm;
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u32 rx_pause_frm;
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u32 rx_multicast;
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u32 rx_broadcast;
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u32 rx_vlan_tag;
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u32 rx_pre_shrink;
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u32 rx_drib_nib;
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u32 rx_unsup_opcd;
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u32 rx_byte;
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u32 tx_unicast;
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u32 tx_pause_frm;
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u32 tx_multicast;
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u32 tx_brdcast;
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u32 tx_vlan_tag;
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u32 tx_bad_fcs;
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u32 tx_jumbo;
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u32 tx_byte;
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};
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struct dnet {
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void __iomem *regs;
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spinlock_t lock;
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struct platform_device *pdev;
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struct net_device *dev;
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struct dnet_stats hw_stats;
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unsigned int capabilities; /* read from FPGA */
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struct napi_struct napi;
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/* PHY stuff */
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struct mii_bus *mii_bus;
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struct phy_device *phy_dev;
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unsigned int link;
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unsigned int speed;
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unsigned int duplex;
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};
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#endif /* _DNET_H */
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