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The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual Tegra124 clock-and-reset controller, so it gets its own node in the device tree. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
80 lines
3.4 KiB
Plaintext
80 lines
3.4 KiB
Plaintext
NVIDIA Tegra124 DFLL FCPU clocksource
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The DFLL IP block on Tegra is a root clocksource designed for clocking
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the fast CPU cluster. It consists of a free-running voltage controlled
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oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
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control module that will automatically adjust the VDD_CPU voltage by
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communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
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Currently only the I2C mode is supported by these bindings.
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Required properties:
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- compatible : should be "nvidia,tegra124-dfll"
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- reg : Defines the following set of registers, in the order listed:
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- registers for the DFLL control logic.
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- registers for the I2C output logic.
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- registers for the integrated I2C master controller.
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- look-up table RAM for voltage register values.
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- interrupts: Should contain the DFLL block interrupt.
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- clocks: Must contain an entry for each entry in clock-names.
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See clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- soc: Clock source for the DFLL control logic.
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- ref: The closed loop reference clock
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- i2c: Clock source for the integrated I2C master.
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- dvco: Reset control for the DFLL DVCO.
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- #clock-cells: Must be 0.
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- clock-output-names: Name of the clock output.
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- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
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hardware will start controlling. The regulator will be queried for
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the I2C register, control values and supported voltages.
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Required properties for the control loop parameters:
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- nvidia,sample-rate: Sample rate of the DFLL control loop.
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- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
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- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
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- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
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- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
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- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
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Optional properties for the control loop parameters:
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- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
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Required properties for I2C mode:
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- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
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Example:
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clock@0,70110000 {
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compatible = "nvidia,tegra124-dfll";
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reg = <0 0x70110000 0 0x100>, /* DFLL control */
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<0 0x70110000 0 0x100>, /* I2C output control */
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<0 0x70110100 0 0x100>, /* Integrated I2C controller */
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<0 0x70110200 0 0x100>; /* Look-up table RAM */
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
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<&tegra_car TEGRA124_CLK_DFLL_REF>,
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<&tegra_car TEGRA124_CLK_I2C5>;
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clock-names = "soc", "ref", "i2c";
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resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
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reset-names = "dvco";
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#clock-cells = <0>;
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clock-output-names = "dfllCPU_out";
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vdd-cpu-supply = <&vdd_cpu>;
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status = "okay";
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nvidia,sample-rate = <12500>;
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nvidia,droop-ctrl = <0x00000f00>;
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nvidia,force-mode = <1>;
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nvidia,cf = <10>;
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nvidia,ci = <0>;
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nvidia,cg = <2>;
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nvidia,i2c-fs-rate = <400000>;
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};
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