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736b1c9c95
The two device tree files octeon_3xxx.dts and octeon_68xx.dts are trimmed by code in a subsequent patch to reflect the hardware actually present on the board. To this end several properties that are not part of the declared bindings are added to aid in trimming off unwanted nodes. Since the device tree and the code that trims it are bound into the kernel binary, these 'marker' properties never escape into the wild, and are purely an implementation detail of the kernel early boot process. This is done for backwards compatibility with existing boards (identified by a board type enumeration value by their bootloaders). New boards will always pass a device tree from the bootloader, the built-in trees are ignored in this case. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/3937/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
20 lines
506 B
Plaintext
20 lines
506 B
Plaintext
* Universal Asynchronous Receiver/Transmitter (UART)
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- compatible: "cavium,octeon-3860-uart"
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Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
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- reg: The base address of the UART register bank.
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- interrupts: A single interrupt specifier.
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- current-speed: Optional, the current bit rate in bits per second.
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Example:
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uart1: serial@1180000000c00 {
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compatible = "cavium,octeon-3860-uart","ns16550";
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reg = <0x11800 0x00000c00 0x0 0x400>;
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current-speed = <115200>;
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interrupts = <0 35>;
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};
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