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fbf6ede2ce
This must be the oldest bug that we have got. Leaving interrupts "as they are" for the R3000 obviously means copying IEp to IEc. Since we have got STATMASK now, I took this opportunity to mask the status register "correctly" for the R3000 now too. Oh, and the R3000 hardly ever is 64-bit. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
516 lines
11 KiB
C
516 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
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* Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
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* Copyright (C) 1999 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_STACKFRAME_H
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#define _ASM_STACKFRAME_H
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#include <linux/threads.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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/*
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* For SMTC kernel, global IE should be left set, and interrupts
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* controlled exclusively via IXMT.
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*/
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#ifdef CONFIG_MIPS_MT_SMTC
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#define STATMASK 0x1e
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#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define STATMASK 0x3f
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#else
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#define STATMASK 0x1f
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif /* CONFIG_MIPS_MT_SMTC */
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.macro SAVE_AT
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.set push
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.set noat
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LONG_S $1, PT_R1(sp)
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.set pop
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.endm
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.macro SAVE_TEMP
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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mflhxu v1
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LONG_S v1, PT_LO(sp)
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mflhxu v1
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LONG_S v1, PT_HI(sp)
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mflhxu v1
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LONG_S v1, PT_ACX(sp)
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#else
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mfhi v1
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LONG_S v1, PT_HI(sp)
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mflo v1
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LONG_S v1, PT_LO(sp)
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#endif
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#ifdef CONFIG_32BIT
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LONG_S $8, PT_R8(sp)
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LONG_S $9, PT_R9(sp)
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#endif
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LONG_S $10, PT_R10(sp)
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LONG_S $11, PT_R11(sp)
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LONG_S $12, PT_R12(sp)
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LONG_S $13, PT_R13(sp)
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LONG_S $14, PT_R14(sp)
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LONG_S $15, PT_R15(sp)
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LONG_S $24, PT_R24(sp)
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.endm
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.macro SAVE_STATIC
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LONG_S $16, PT_R16(sp)
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LONG_S $17, PT_R17(sp)
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LONG_S $18, PT_R18(sp)
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LONG_S $19, PT_R19(sp)
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LONG_S $20, PT_R20(sp)
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LONG_S $21, PT_R21(sp)
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LONG_S $22, PT_R22(sp)
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LONG_S $23, PT_R23(sp)
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LONG_S $30, PT_R30(sp)
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.endm
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#ifdef CONFIG_SMP
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#ifdef CONFIG_MIPS_MT_SMTC
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#define PTEBASE_SHIFT 19 /* TCBIND */
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#else
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#define PTEBASE_SHIFT 23 /* CONTEXT */
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#endif
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.macro get_saved_sp /* SMP variation */
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#ifdef CONFIG_MIPS_MT_SMTC
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mfc0 k0, CP0_TCBIND
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#else
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MFC0 k0, CP0_CONTEXT
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#endif
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#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
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lui k1, %highest(kernelsp)
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daddiu k1, %higher(kernelsp)
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dsll k1, 16
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daddiu k1, %hi(kernelsp)
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dsll k1, 16
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#else
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lui k1, %hi(kernelsp)
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#endif
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LONG_SRL k0, PTEBASE_SHIFT
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LONG_ADDU k1, k0
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LONG_L k1, %lo(kernelsp)(k1)
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.endm
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.macro set_saved_sp stackp temp temp2
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#ifdef CONFIG_MIPS_MT_SMTC
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mfc0 \temp, CP0_TCBIND
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#else
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MFC0 \temp, CP0_CONTEXT
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#endif
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LONG_SRL \temp, PTEBASE_SHIFT
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LONG_S \stackp, kernelsp(\temp)
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.endm
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#else
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.macro get_saved_sp /* Uniprocessor variation */
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#if defined(CONFIG_BUILD_ELF64) || (defined(CONFIG_64BIT) && __GNUC__ < 4)
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lui k1, %highest(kernelsp)
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daddiu k1, %higher(kernelsp)
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dsll k1, k1, 16
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daddiu k1, %hi(kernelsp)
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dsll k1, k1, 16
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#else
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lui k1, %hi(kernelsp)
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#endif
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LONG_L k1, %lo(kernelsp)(k1)
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.endm
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.macro set_saved_sp stackp temp temp2
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LONG_S \stackp, kernelsp
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.endm
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#endif
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.macro SAVE_SOME
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.set push
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.set noat
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.set reorder
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mfc0 k0, CP0_STATUS
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sll k0, 3 /* extract cu0 bit */
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.set noreorder
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bltz k0, 8f
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move k1, sp
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.set reorder
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/* Called from user mode, new stack. */
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get_saved_sp
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8: move k0, sp
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PTR_SUBU sp, k1, PT_SIZE
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LONG_S k0, PT_R29(sp)
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LONG_S $3, PT_R3(sp)
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/*
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* You might think that you don't need to save $0,
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* but the FPU emulator and gdb remote debug stub
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* need it to operate correctly
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*/
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LONG_S $0, PT_R0(sp)
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mfc0 v1, CP0_STATUS
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LONG_S $2, PT_R2(sp)
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LONG_S v1, PT_STATUS(sp)
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* Ideally, these instructions would be shuffled in
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* to cover the pipeline delay.
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*/
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.set mips32
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mfc0 v1, CP0_TCSTATUS
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.set mips0
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LONG_S v1, PT_TCSTATUS(sp)
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#endif /* CONFIG_MIPS_MT_SMTC */
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LONG_S $4, PT_R4(sp)
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mfc0 v1, CP0_CAUSE
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LONG_S $5, PT_R5(sp)
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LONG_S v1, PT_CAUSE(sp)
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LONG_S $6, PT_R6(sp)
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MFC0 v1, CP0_EPC
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LONG_S $7, PT_R7(sp)
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#ifdef CONFIG_64BIT
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LONG_S $8, PT_R8(sp)
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LONG_S $9, PT_R9(sp)
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#endif
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LONG_S v1, PT_EPC(sp)
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LONG_S $25, PT_R25(sp)
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LONG_S $28, PT_R28(sp)
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LONG_S $31, PT_R31(sp)
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ori $28, sp, _THREAD_MASK
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xori $28, _THREAD_MASK
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.set pop
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.endm
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.macro SAVE_ALL
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SAVE_SOME
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SAVE_AT
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SAVE_TEMP
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SAVE_STATIC
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.endm
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.macro RESTORE_AT
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.set push
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.set noat
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LONG_L $1, PT_R1(sp)
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.set pop
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.endm
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.macro RESTORE_TEMP
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#ifdef CONFIG_CPU_HAS_SMARTMIPS
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LONG_L $24, PT_ACX(sp)
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mtlhx $24
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LONG_L $24, PT_HI(sp)
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mtlhx $24
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LONG_L $24, PT_LO(sp)
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mtlhx $24
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#else
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LONG_L $24, PT_LO(sp)
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mtlo $24
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LONG_L $24, PT_HI(sp)
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mthi $24
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#endif
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#ifdef CONFIG_32BIT
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LONG_L $8, PT_R8(sp)
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LONG_L $9, PT_R9(sp)
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#endif
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LONG_L $10, PT_R10(sp)
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LONG_L $11, PT_R11(sp)
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LONG_L $12, PT_R12(sp)
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LONG_L $13, PT_R13(sp)
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LONG_L $14, PT_R14(sp)
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LONG_L $15, PT_R15(sp)
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LONG_L $24, PT_R24(sp)
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.endm
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.macro RESTORE_STATIC
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LONG_L $16, PT_R16(sp)
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LONG_L $17, PT_R17(sp)
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LONG_L $18, PT_R18(sp)
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LONG_L $19, PT_R19(sp)
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LONG_L $20, PT_R20(sp)
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LONG_L $21, PT_R21(sp)
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LONG_L $22, PT_R22(sp)
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LONG_L $23, PT_R23(sp)
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LONG_L $30, PT_R30(sp)
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.endm
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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.macro RESTORE_SOME
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.set push
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.set reorder
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.set noat
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mfc0 a0, CP0_STATUS
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li v1, 0xff00
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ori a0, STATMASK
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xori a0, STATMASK
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mtc0 a0, CP0_STATUS
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and a0, v1
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LONG_L v0, PT_STATUS(sp)
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nor v1, $0, v1
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and v0, v1
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or v0, a0
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mtc0 v0, CP0_STATUS
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LONG_L $31, PT_R31(sp)
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LONG_L $28, PT_R28(sp)
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LONG_L $25, PT_R25(sp)
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LONG_L $7, PT_R7(sp)
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LONG_L $6, PT_R6(sp)
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LONG_L $5, PT_R5(sp)
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LONG_L $4, PT_R4(sp)
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LONG_L $3, PT_R3(sp)
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LONG_L $2, PT_R2(sp)
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.set pop
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.endm
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.macro RESTORE_SP_AND_RET
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.set push
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.set noreorder
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LONG_L k0, PT_EPC(sp)
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LONG_L sp, PT_R29(sp)
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jr k0
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rfe
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.set pop
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.endm
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#else
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.macro RESTORE_SOME
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.set push
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.set reorder
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.set noat
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#ifdef CONFIG_MIPS_MT_SMTC
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.set mips32r2
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/*
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* This may not really be necessary if ints are already
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* inhibited here.
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*/
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mfc0 v0, CP0_TCSTATUS
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ori v0, TCSTATUS_IXMT
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mtc0 v0, CP0_TCSTATUS
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_ehb
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DMT 5 # dmt a1
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jal mips_ihb
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 a0, CP0_STATUS
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ori a0, STATMASK
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xori a0, STATMASK
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mtc0 a0, CP0_STATUS
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li v1, 0xff00
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and a0, v1
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LONG_L v0, PT_STATUS(sp)
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nor v1, $0, v1
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and v0, v1
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or v0, a0
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mtc0 v0, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* Only after EXL/ERL have been restored to status can we
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* restore TCStatus.IXMT.
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*/
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LONG_L v1, PT_TCSTATUS(sp)
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_ehb
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mfc0 v0, CP0_TCSTATUS
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andi v1, TCSTATUS_IXMT
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/* We know that TCStatua.IXMT should be set from above */
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xori v0, v0, TCSTATUS_IXMT
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or v0, v0, v1
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mtc0 v0, CP0_TCSTATUS
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_ehb
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andi a1, a1, VPECONTROL_TE
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beqz a1, 1f
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emt
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1:
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.set mips0
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#endif /* CONFIG_MIPS_MT_SMTC */
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LONG_L v1, PT_EPC(sp)
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MTC0 v1, CP0_EPC
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LONG_L $31, PT_R31(sp)
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LONG_L $28, PT_R28(sp)
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LONG_L $25, PT_R25(sp)
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#ifdef CONFIG_64BIT
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LONG_L $8, PT_R8(sp)
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LONG_L $9, PT_R9(sp)
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#endif
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LONG_L $7, PT_R7(sp)
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LONG_L $6, PT_R6(sp)
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LONG_L $5, PT_R5(sp)
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LONG_L $4, PT_R4(sp)
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LONG_L $3, PT_R3(sp)
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LONG_L $2, PT_R2(sp)
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.set pop
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.endm
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.macro RESTORE_SP_AND_RET
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LONG_L sp, PT_R29(sp)
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.set mips3
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eret
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.set mips0
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.endm
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#endif
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.macro RESTORE_SP
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LONG_L sp, PT_R29(sp)
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.endm
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.macro RESTORE_ALL
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RESTORE_TEMP
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RESTORE_STATIC
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RESTORE_AT
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RESTORE_SOME
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RESTORE_SP
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.endm
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.macro RESTORE_ALL_AND_RET
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RESTORE_TEMP
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RESTORE_STATIC
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RESTORE_AT
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RESTORE_SOME
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RESTORE_SP_AND_RET
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.endm
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/*
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* Move to kernel mode and disable interrupts.
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro CLI
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#if !defined(CONFIG_MIPS_MT_SMTC)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | STATMASK
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or t0, t1
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xori t0, STATMASK
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mtc0 t0, CP0_STATUS
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#else /* CONFIG_MIPS_MT_SMTC */
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/*
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* For SMTC, we need to set privilege
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* and disable interrupts only for the
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* current TC, using the TCStatus register.
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*/
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mfc0 t0,CP0_TCSTATUS
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/* Fortunately CU 0 is in the same place in both registers */
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/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
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li t1, ST0_CU0 | 0x08001c00
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or t0,t1
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/* Clear TKSU, leave IXMT */
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xori t0, 0x00001800
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mtc0 t0, CP0_TCSTATUS
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_ehb
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/* We need to leave the global IE bit set, but clear EXL...*/
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mfc0 t0, CP0_STATUS
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ori t0, ST0_EXL | ST0_ERL
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xori t0, ST0_EXL | ST0_ERL
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mtc0 t0, CP0_STATUS
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_disable_hazard
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.endm
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/*
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* Move to kernel mode and enable interrupts.
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro STI
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#if !defined(CONFIG_MIPS_MT_SMTC)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | STATMASK
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or t0, t1
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xori t0, STATMASK & ~1
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mtc0 t0, CP0_STATUS
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#else /* CONFIG_MIPS_MT_SMTC */
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/*
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* For SMTC, we need to set privilege
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* and enable interrupts only for the
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* current TC, using the TCStatus register.
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*/
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_ehb
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mfc0 t0,CP0_TCSTATUS
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/* Fortunately CU 0 is in the same place in both registers */
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/* Set TCU0, TKSU (for later inversion) and IXMT */
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li t1, ST0_CU0 | 0x08001c00
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or t0,t1
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/* Clear TKSU *and* IXMT */
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xori t0, 0x00001c00
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mtc0 t0, CP0_TCSTATUS
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_ehb
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/* We need to leave the global IE bit set, but clear EXL...*/
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mfc0 t0, CP0_STATUS
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ori t0, ST0_EXL
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xori t0, ST0_EXL
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mtc0 t0, CP0_STATUS
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/* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_enable_hazard
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.endm
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/*
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* Just move to kernel mode and leave interrupts as they are. Note
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* for the R3000 this means copying the previous enable from IEp.
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro KMODE
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* This gets baroque in SMTC. We want to
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* protect the non-atomic clearing of EXL
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* with DMT/EMT, but we don't want to take
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* an interrupt while DMT is still in effect.
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*/
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/* KMODE gets invoked from both reorder and noreorder code */
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.set push
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.set mips32r2
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.set noreorder
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mfc0 v0, CP0_TCSTATUS
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andi v1, v0, TCSTATUS_IXMT
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ori v0, TCSTATUS_IXMT
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mtc0 v0, CP0_TCSTATUS
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_ehb
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DMT 2 # dmt v0
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/*
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* We don't know a priori if ra is "live"
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*/
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move t0, ra
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jal mips_ihb
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nop /* delay slot */
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move ra, t0
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | (STATMASK & ~1)
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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andi t2, t0, ST0_IEP
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srl t2, 2
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or t0, t2
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#endif
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or t0, t1
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xori t0, STATMASK & ~1
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mtc0 t0, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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_ehb
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andi v0, v0, VPECONTROL_TE
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|
beqz v0, 2f
|
|
nop /* delay slot */
|
|
emt
|
|
2:
|
|
mfc0 v0, CP0_TCSTATUS
|
|
/* Clear IXMT, then OR in previous value */
|
|
ori v0, TCSTATUS_IXMT
|
|
xori v0, TCSTATUS_IXMT
|
|
or v0, v1, v0
|
|
mtc0 v0, CP0_TCSTATUS
|
|
/*
|
|
* irq_disable_hazard below should expand to EHB
|
|
* on 24K/34K CPUS
|
|
*/
|
|
.set pop
|
|
#endif /* CONFIG_MIPS_MT_SMTC */
|
|
irq_disable_hazard
|
|
.endm
|
|
|
|
#endif /* _ASM_STACKFRAME_H */
|