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65a27a3510
Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Link: http://lkml.kernel.org/r/1455098123-11740-17-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
242 lines
5.4 KiB
C
242 lines
5.4 KiB
C
#include <linux/perf_event.h>
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enum perf_msr_id {
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PERF_MSR_TSC = 0,
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PERF_MSR_APERF = 1,
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PERF_MSR_MPERF = 2,
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PERF_MSR_PPERF = 3,
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PERF_MSR_SMI = 4,
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PERF_MSR_EVENT_MAX,
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};
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static bool test_aperfmperf(int idx)
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{
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return boot_cpu_has(X86_FEATURE_APERFMPERF);
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}
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static bool test_intel(int idx)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
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boot_cpu_data.x86 != 6)
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return false;
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switch (boot_cpu_data.x86_model) {
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case 30: /* 45nm Nehalem */
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case 26: /* 45nm Nehalem-EP */
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case 46: /* 45nm Nehalem-EX */
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case 37: /* 32nm Westmere */
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case 44: /* 32nm Westmere-EP */
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case 47: /* 32nm Westmere-EX */
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case 42: /* 32nm SandyBridge */
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case 45: /* 32nm SandyBridge-E/EN/EP */
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case 58: /* 22nm IvyBridge */
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case 62: /* 22nm IvyBridge-EP/EX */
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case 60: /* 22nm Haswell Core */
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case 63: /* 22nm Haswell Server */
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case 69: /* 22nm Haswell ULT */
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case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
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case 61: /* 14nm Broadwell Core-M */
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case 86: /* 14nm Broadwell Xeon D */
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case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
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case 79: /* 14nm Broadwell Server */
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case 55: /* 22nm Atom "Silvermont" */
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case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
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case 76: /* 14nm Atom "Airmont" */
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if (idx == PERF_MSR_SMI)
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return true;
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break;
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case 78: /* 14nm Skylake Mobile */
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case 94: /* 14nm Skylake Desktop */
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if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
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return true;
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break;
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}
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return false;
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}
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struct perf_msr {
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u64 msr;
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struct perf_pmu_events_attr *attr;
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bool (*test)(int idx);
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};
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PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00");
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PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
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PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
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PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
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PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04");
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static struct perf_msr msr[] = {
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[PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, },
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[PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, },
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[PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, },
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[PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, },
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[PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, },
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};
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static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
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NULL,
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};
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static struct attribute_group events_attr_group = {
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.name = "events",
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.attrs = events_attrs,
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};
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PMU_FORMAT_ATTR(event, "config:0-63");
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static struct attribute *format_attrs[] = {
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&format_attr_event.attr,
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NULL,
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};
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static struct attribute_group format_attr_group = {
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.name = "format",
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.attrs = format_attrs,
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};
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static const struct attribute_group *attr_groups[] = {
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&events_attr_group,
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&format_attr_group,
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NULL,
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};
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static int msr_event_init(struct perf_event *event)
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{
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u64 cfg = event->attr.config;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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if (cfg >= PERF_MSR_EVENT_MAX)
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return -EINVAL;
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/* unsupported modes and filters */
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if (event->attr.exclude_user ||
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event->attr.exclude_kernel ||
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event->attr.exclude_hv ||
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event->attr.exclude_idle ||
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event->attr.exclude_host ||
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event->attr.exclude_guest ||
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event->attr.sample_period) /* no sampling */
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return -EINVAL;
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if (!msr[cfg].attr)
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return -EINVAL;
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event->hw.idx = -1;
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event->hw.event_base = msr[cfg].msr;
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event->hw.config = cfg;
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return 0;
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}
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static inline u64 msr_read_counter(struct perf_event *event)
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{
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u64 now;
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if (event->hw.event_base)
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rdmsrl(event->hw.event_base, now);
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else
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rdtscll(now);
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return now;
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}
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static void msr_event_update(struct perf_event *event)
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{
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u64 prev, now;
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s64 delta;
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/* Careful, an NMI might modify the previous event value. */
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again:
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prev = local64_read(&event->hw.prev_count);
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now = msr_read_counter(event);
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if (local64_cmpxchg(&event->hw.prev_count, prev, now) != prev)
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goto again;
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delta = now - prev;
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if (unlikely(event->hw.event_base == MSR_SMI_COUNT))
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delta = sign_extend64(delta, 31);
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local64_add(now - prev, &event->count);
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}
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static void msr_event_start(struct perf_event *event, int flags)
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{
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u64 now;
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now = msr_read_counter(event);
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local64_set(&event->hw.prev_count, now);
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}
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static void msr_event_stop(struct perf_event *event, int flags)
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{
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msr_event_update(event);
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}
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static void msr_event_del(struct perf_event *event, int flags)
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{
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msr_event_stop(event, PERF_EF_UPDATE);
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}
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static int msr_event_add(struct perf_event *event, int flags)
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{
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if (flags & PERF_EF_START)
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msr_event_start(event, flags);
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return 0;
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}
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static struct pmu pmu_msr = {
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.task_ctx_nr = perf_sw_context,
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.attr_groups = attr_groups,
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.event_init = msr_event_init,
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.add = msr_event_add,
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.del = msr_event_del,
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.start = msr_event_start,
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.stop = msr_event_stop,
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.read = msr_event_update,
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.capabilities = PERF_PMU_CAP_NO_INTERRUPT,
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};
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static int __init msr_init(void)
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{
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int i, j = 0;
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if (!boot_cpu_has(X86_FEATURE_TSC)) {
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pr_cont("no MSR PMU driver.\n");
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return 0;
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}
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/* Probe the MSRs. */
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for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
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u64 val;
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/*
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* Virt sucks arse; you cannot tell if a R/O MSR is present :/
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*/
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if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
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msr[i].attr = NULL;
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}
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/* List remaining MSRs in the sysfs attrs. */
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for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
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if (msr[i].attr)
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events_attrs[j++] = &msr[i].attr->attr.attr;
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}
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events_attrs[j] = NULL;
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perf_pmu_register(&pmu_msr, "msr", -1);
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return 0;
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}
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device_initcall(msr_init);
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