mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 12:43:55 +08:00
79f5599772
Remove open-coded zalloc_cpumask_var() and zalloc_cpumask_var_node(). Signed-off-by: Li Zefan <lizf@cn.fujitsu.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
613 lines
14 KiB
C
613 lines
14 KiB
C
#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/prctl.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/pm.h>
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#include <linux/clockchips.h>
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#include <linux/random.h>
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#include <trace/events/power.h>
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#include <asm/system.h>
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#include <asm/apic.h>
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#include <asm/syscalls.h>
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#include <asm/idle.h>
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#include <asm/uaccess.h>
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#include <asm/i387.h>
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#include <asm/ds.h>
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unsigned long idle_halt;
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EXPORT_SYMBOL(idle_halt);
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unsigned long idle_nomwait;
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EXPORT_SYMBOL(idle_nomwait);
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struct kmem_cache *task_xstate_cachep;
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
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{
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*dst = *src;
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if (src->thread.xstate) {
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dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
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GFP_KERNEL);
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if (!dst->thread.xstate)
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return -ENOMEM;
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WARN_ON((unsigned long)dst->thread.xstate & 15);
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memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
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}
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return 0;
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}
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void free_thread_xstate(struct task_struct *tsk)
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{
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if (tsk->thread.xstate) {
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kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
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tsk->thread.xstate = NULL;
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}
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WARN(tsk->thread.ds_ctx, "leaking DS context\n");
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}
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void free_thread_info(struct thread_info *ti)
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{
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free_thread_xstate(ti->task);
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free_pages((unsigned long)ti, get_order(THREAD_SIZE));
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}
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void arch_task_cache_init(void)
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{
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task_xstate_cachep =
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kmem_cache_create("task_xstate", xstate_size,
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__alignof__(union thread_xstate),
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SLAB_PANIC | SLAB_NOTRACK, NULL);
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}
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/*
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* Free current thread data structures etc..
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*/
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void exit_thread(void)
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{
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struct task_struct *me = current;
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struct thread_struct *t = &me->thread;
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unsigned long *bp = t->io_bitmap_ptr;
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if (bp) {
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struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
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t->io_bitmap_ptr = NULL;
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clear_thread_flag(TIF_IO_BITMAP);
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/*
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* Careful, clear this in the TSS too:
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*/
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memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
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t->io_bitmap_max = 0;
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put_cpu();
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kfree(bp);
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}
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}
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void flush_thread(void)
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{
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struct task_struct *tsk = current;
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#ifdef CONFIG_X86_64
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if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
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clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
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if (test_tsk_thread_flag(tsk, TIF_IA32)) {
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clear_tsk_thread_flag(tsk, TIF_IA32);
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} else {
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set_tsk_thread_flag(tsk, TIF_IA32);
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current_thread_info()->status |= TS_COMPAT;
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}
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}
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#endif
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clear_tsk_thread_flag(tsk, TIF_DEBUG);
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tsk->thread.debugreg0 = 0;
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tsk->thread.debugreg1 = 0;
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tsk->thread.debugreg2 = 0;
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tsk->thread.debugreg3 = 0;
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tsk->thread.debugreg6 = 0;
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tsk->thread.debugreg7 = 0;
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memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
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/*
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* Forget coprocessor state..
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*/
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tsk->fpu_counter = 0;
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clear_fpu(tsk);
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clear_used_math();
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}
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static void hard_disable_TSC(void)
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{
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write_cr4(read_cr4() | X86_CR4_TSD);
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}
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void disable_TSC(void)
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{
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preempt_disable();
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if (!test_and_set_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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hard_disable_TSC();
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preempt_enable();
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}
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static void hard_enable_TSC(void)
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{
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write_cr4(read_cr4() & ~X86_CR4_TSD);
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}
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static void enable_TSC(void)
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{
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preempt_disable();
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if (test_and_clear_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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hard_enable_TSC();
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preempt_enable();
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}
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int get_tsc_mode(unsigned long adr)
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{
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unsigned int val;
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if (test_thread_flag(TIF_NOTSC))
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val = PR_TSC_SIGSEGV;
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else
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val = PR_TSC_ENABLE;
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return put_user(val, (unsigned int __user *)adr);
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}
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int set_tsc_mode(unsigned int val)
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{
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if (val == PR_TSC_SIGSEGV)
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disable_TSC();
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else if (val == PR_TSC_ENABLE)
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enable_TSC();
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else
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return -EINVAL;
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return 0;
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}
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void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
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struct tss_struct *tss)
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{
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struct thread_struct *prev, *next;
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prev = &prev_p->thread;
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next = &next_p->thread;
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if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
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test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
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ds_switch_to(prev_p, next_p);
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else if (next->debugctlmsr != prev->debugctlmsr)
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update_debugctlmsr(next->debugctlmsr);
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if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
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set_debugreg(next->debugreg0, 0);
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set_debugreg(next->debugreg1, 1);
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set_debugreg(next->debugreg2, 2);
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set_debugreg(next->debugreg3, 3);
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/* no 4 and 5 */
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set_debugreg(next->debugreg6, 6);
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set_debugreg(next->debugreg7, 7);
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}
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if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
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test_tsk_thread_flag(next_p, TIF_NOTSC)) {
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/* prev and next are different */
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if (test_tsk_thread_flag(next_p, TIF_NOTSC))
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hard_disable_TSC();
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else
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hard_enable_TSC();
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}
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if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
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/*
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* Copy the relevant range of the IO bitmap.
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* Normally this is 128 bytes or less:
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*/
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memcpy(tss->io_bitmap, next->io_bitmap_ptr,
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max(prev->io_bitmap_max, next->io_bitmap_max));
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} else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
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/*
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* Clear any possible leftover bits:
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*/
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memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
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}
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}
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int sys_fork(struct pt_regs *regs)
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{
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return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
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}
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/*
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* This is trivial, and on the face of it looks like it
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* could equally well be done in user mode.
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*
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* Not so, for quite unobvious reasons - register pressure.
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* In user mode vfork() cannot have a stack frame, and if
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* done by calling the "clone()" system call directly, you
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* do not have enough call-clobbered registers to hold all
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* the information you need.
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*/
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int sys_vfork(struct pt_regs *regs)
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{
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return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
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NULL, NULL);
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}
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/*
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* Idle related variables and functions
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*/
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unsigned long boot_option_idle_override = 0;
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EXPORT_SYMBOL(boot_option_idle_override);
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/*
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* Powermanagement idle function, if any..
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*/
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void (*pm_idle)(void);
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EXPORT_SYMBOL(pm_idle);
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#ifdef CONFIG_X86_32
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/*
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* This halt magic was a workaround for ancient floppy DMA
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* wreckage. It should be safe to remove.
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*/
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static int hlt_counter;
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void disable_hlt(void)
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{
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hlt_counter++;
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}
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EXPORT_SYMBOL(disable_hlt);
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void enable_hlt(void)
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{
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hlt_counter--;
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}
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EXPORT_SYMBOL(enable_hlt);
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static inline int hlt_use_halt(void)
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{
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return (!hlt_counter && boot_cpu_data.hlt_works_ok);
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}
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#else
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static inline int hlt_use_halt(void)
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{
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return 1;
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}
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#endif
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/*
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* We use this if we don't have any better
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* idle routine..
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*/
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void default_idle(void)
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{
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if (hlt_use_halt()) {
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trace_power_start(POWER_CSTATE, 1);
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current_thread_info()->status &= ~TS_POLLING;
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/*
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* TS_POLLING-cleared state must be visible before we
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* test NEED_RESCHED:
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*/
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smp_mb();
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if (!need_resched())
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safe_halt(); /* enables interrupts racelessly */
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else
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local_irq_enable();
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current_thread_info()->status |= TS_POLLING;
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} else {
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local_irq_enable();
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/* loop is done by the caller */
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cpu_relax();
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}
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}
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#ifdef CONFIG_APM_MODULE
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EXPORT_SYMBOL(default_idle);
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#endif
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void stop_this_cpu(void *dummy)
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{
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local_irq_disable();
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/*
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* Remove this CPU:
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*/
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set_cpu_online(smp_processor_id(), false);
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disable_local_APIC();
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for (;;) {
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if (hlt_works(smp_processor_id()))
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halt();
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}
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}
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static void do_nothing(void *unused)
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{
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}
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/*
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* cpu_idle_wait - Used to ensure that all the CPUs discard old value of
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* pm_idle and update to new pm_idle value. Required while changing pm_idle
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* handler on SMP systems.
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*
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* Caller must have changed pm_idle to the new value before the call. Old
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* pm_idle value will not be used by any CPU after the return of this function.
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*/
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void cpu_idle_wait(void)
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{
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smp_mb();
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/* kick all the CPUs so that they exit out of pm_idle */
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smp_call_function(do_nothing, NULL, 1);
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}
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EXPORT_SYMBOL_GPL(cpu_idle_wait);
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/*
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* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
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* which can obviate IPI to trigger checking of need_resched.
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* We execute MONITOR against need_resched and enter optimized wait state
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* through MWAIT. Whenever someone changes need_resched, we would be woken
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* up from MWAIT (without an IPI).
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*
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* New with Core Duo processors, MWAIT can take some hints based on CPU
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* capability.
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*/
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void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
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{
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trace_power_start(POWER_CSTATE, (ax>>4)+1);
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if (!need_resched()) {
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if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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__mwait(ax, cx);
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}
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}
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/* Default MONITOR/MWAIT with no hints, used for default C1 state */
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static void mwait_idle(void)
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{
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if (!need_resched()) {
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trace_power_start(POWER_CSTATE, 1);
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if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
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clflush((void *)¤t_thread_info()->flags);
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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smp_mb();
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if (!need_resched())
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__sti_mwait(0, 0);
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else
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local_irq_enable();
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} else
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local_irq_enable();
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}
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/*
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* On SMP it's slightly faster (but much more power-consuming!)
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* to poll the ->work.need_resched flag instead of waiting for the
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* cross-CPU IPI to arrive. Use this option with caution.
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*/
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static void poll_idle(void)
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{
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trace_power_start(POWER_CSTATE, 0);
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local_irq_enable();
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while (!need_resched())
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cpu_relax();
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trace_power_end(0);
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}
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/*
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* mwait selection logic:
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*
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* It depends on the CPU. For AMD CPUs that support MWAIT this is
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* wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
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* then depend on a clock divisor and current Pstate of the core. If
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* all cores of a processor are in halt state (C1) the processor can
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* enter the C1E (C1 enhanced) state. If mwait is used this will never
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* happen.
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*
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* idle=mwait overrides this decision and forces the usage of mwait.
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*/
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static int __cpuinitdata force_mwait;
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#define MWAIT_INFO 0x05
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#define MWAIT_ECX_EXTENDED_INFO 0x01
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#define MWAIT_EDX_C1 0xf0
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static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
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{
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u32 eax, ebx, ecx, edx;
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if (force_mwait)
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return 1;
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if (c->cpuid_level < MWAIT_INFO)
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return 0;
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cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
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/* Check, whether EDX has extended info about MWAIT */
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if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
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return 1;
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/*
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* edx enumeratios MONITOR/MWAIT extensions. Check, whether
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* C1 supports MWAIT
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*/
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return (edx & MWAIT_EDX_C1);
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}
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/*
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* Check for AMD CPUs, which have potentially C1E support
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*/
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static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
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{
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if (c->x86_vendor != X86_VENDOR_AMD)
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return 0;
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if (c->x86 < 0x0F)
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return 0;
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/* Family 0x0f models < rev F do not have C1E */
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if (c->x86 == 0x0f && c->x86_model < 0x40)
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return 0;
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return 1;
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}
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static cpumask_var_t c1e_mask;
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static int c1e_detected;
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void c1e_remove_cpu(int cpu)
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{
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if (c1e_mask != NULL)
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cpumask_clear_cpu(cpu, c1e_mask);
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}
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/*
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* C1E aware idle routine. We check for C1E active in the interrupt
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* pending message MSR. If we detect C1E, then we handle it the same
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* way as C3 power states (local apic timer and TSC stop)
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*/
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static void c1e_idle(void)
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{
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if (need_resched())
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return;
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if (!c1e_detected) {
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u32 lo, hi;
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rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
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if (lo & K8_INTP_C1E_ACTIVE_MASK) {
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c1e_detected = 1;
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if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
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mark_tsc_unstable("TSC halt in AMD C1E");
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printk(KERN_INFO "System has AMD C1E enabled\n");
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set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
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}
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}
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if (c1e_detected) {
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int cpu = smp_processor_id();
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if (!cpumask_test_cpu(cpu, c1e_mask)) {
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cpumask_set_cpu(cpu, c1e_mask);
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/*
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* Force broadcast so ACPI can not interfere.
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*/
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
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&cpu);
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printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
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cpu);
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}
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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default_idle();
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/*
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* The switch back from broadcast mode needs to be
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* called with interrupts disabled.
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|
*/
|
|
local_irq_disable();
|
|
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
|
|
local_irq_enable();
|
|
} else
|
|
default_idle();
|
|
}
|
|
|
|
void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
if (pm_idle == poll_idle && smp_num_siblings > 1) {
|
|
printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
|
|
" performance may degrade.\n");
|
|
}
|
|
#endif
|
|
if (pm_idle)
|
|
return;
|
|
|
|
if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
|
|
/*
|
|
* One CPU supports mwait => All CPUs supports mwait
|
|
*/
|
|
printk(KERN_INFO "using mwait in idle threads.\n");
|
|
pm_idle = mwait_idle;
|
|
} else if (check_c1e_idle(c)) {
|
|
printk(KERN_INFO "using C1E aware idle routine\n");
|
|
pm_idle = c1e_idle;
|
|
} else
|
|
pm_idle = default_idle;
|
|
}
|
|
|
|
void __init init_c1e_mask(void)
|
|
{
|
|
/* If we're using c1e_idle, we need to allocate c1e_mask. */
|
|
if (pm_idle == c1e_idle)
|
|
zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
|
|
}
|
|
|
|
static int __init idle_setup(char *str)
|
|
{
|
|
if (!str)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(str, "poll")) {
|
|
printk("using polling idle threads.\n");
|
|
pm_idle = poll_idle;
|
|
} else if (!strcmp(str, "mwait"))
|
|
force_mwait = 1;
|
|
else if (!strcmp(str, "halt")) {
|
|
/*
|
|
* When the boot option of idle=halt is added, halt is
|
|
* forced to be used for CPU idle. In such case CPU C2/C3
|
|
* won't be used again.
|
|
* To continue to load the CPU idle driver, don't touch
|
|
* the boot_option_idle_override.
|
|
*/
|
|
pm_idle = default_idle;
|
|
idle_halt = 1;
|
|
return 0;
|
|
} else if (!strcmp(str, "nomwait")) {
|
|
/*
|
|
* If the boot option of "idle=nomwait" is added,
|
|
* it means that mwait will be disabled for CPU C2/C3
|
|
* states. In such case it won't touch the variable
|
|
* of boot_option_idle_override.
|
|
*/
|
|
idle_nomwait = 1;
|
|
return 0;
|
|
} else
|
|
return -1;
|
|
|
|
boot_option_idle_override = 1;
|
|
return 0;
|
|
}
|
|
early_param("idle", idle_setup);
|
|
|
|
unsigned long arch_align_stack(unsigned long sp)
|
|
{
|
|
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
|
sp -= get_random_int() % 8192;
|
|
return sp & ~0xf;
|
|
}
|
|
|
|
unsigned long arch_randomize_brk(struct mm_struct *mm)
|
|
{
|
|
unsigned long range_end = mm->brk + 0x02000000;
|
|
return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
|
|
}
|
|
|