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f4e6698329
Support PXA168/PXA910/MMP2 pinmux. Now only support function switch. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> [Rebase and fix some whitespace issues] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
265 lines
3.8 KiB
C
265 lines
3.8 KiB
C
/*
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* linux/drivers/pinctrl/pinctrl-pxa3xx.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*
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* Copyright (C) 2011, Marvell Technology Group Ltd.
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*
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* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
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*
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*/
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#ifndef __PINCTRL_PXA3XX_H
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
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#define PXA3xx_MUX_GPIO 0
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#define PXA3xx_MAX_MUX 8
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#define MFPR_FUNC_MASK 0x7
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enum pxa_cpu_type {
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PINCTRL_INVALID = 0,
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PINCTRL_PXA300,
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PINCTRL_PXA310,
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PINCTRL_PXA320,
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PINCTRL_PXA168,
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PINCTRL_PXA910,
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PINCTRL_PXA930,
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PINCTRL_PXA955,
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PINCTRL_MMP2,
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PINCTRL_MAX,
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};
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struct pxa3xx_mfp_pin {
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const char *name;
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const unsigned int pin;
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const unsigned int mfpr; /* register offset */
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const unsigned short func[8];
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};
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struct pxa3xx_pin_group {
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const char *name;
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const unsigned mux;
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const unsigned *pins;
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const unsigned npins;
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};
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struct pxa3xx_pmx_func {
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const char *name;
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const char * const * groups;
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const unsigned num_groups;
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};
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struct pxa3xx_pinmux_info {
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struct device *dev;
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struct pinctrl_dev *pctrl;
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enum pxa_cpu_type cputype;
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unsigned int phy_base;
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unsigned int phy_size;
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void __iomem *virt_base;
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struct pxa3xx_mfp_pin *mfp;
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unsigned int num_mfp;
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struct pxa3xx_pin_group *grps;
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unsigned int num_grps;
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struct pxa3xx_pmx_func *funcs;
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unsigned int num_funcs;
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unsigned int num_gpio;
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struct pinctrl_desc *desc;
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struct pinctrl_pin_desc *pads;
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unsigned int num_pads;
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unsigned ds_mask; /* drive strength mask */
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unsigned ds_shift; /* drive strength shift */
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unsigned slp_mask; /* sleep mask */
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unsigned slp_input_low;
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unsigned slp_input_high;
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unsigned slp_output_low;
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unsigned slp_output_high;
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unsigned slp_float;
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};
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enum pxa3xx_pin_list {
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GPIO0 = 0,
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GPIO1,
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GPIO2,
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GPIO3,
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GPIO4,
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GPIO5,
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GPIO6,
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GPIO7,
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GPIO8,
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GPIO9,
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GPIO10, /* 10 */
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GPIO11,
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GPIO12,
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GPIO13,
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GPIO14,
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GPIO15,
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GPIO16,
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GPIO17,
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GPIO18,
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GPIO19,
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GPIO20, /* 20 */
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GPIO21,
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GPIO22,
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GPIO23,
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GPIO24,
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GPIO25,
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GPIO26,
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GPIO27,
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GPIO28,
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GPIO29,
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GPIO30, /* 30 */
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GPIO31,
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GPIO32,
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GPIO33,
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GPIO34,
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GPIO35,
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GPIO36,
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GPIO37,
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GPIO38,
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GPIO39,
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GPIO40, /* 40 */
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GPIO41,
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GPIO42,
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GPIO43,
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GPIO44,
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GPIO45,
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GPIO46,
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GPIO47,
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GPIO48,
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GPIO49,
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GPIO50, /* 50 */
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GPIO51,
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GPIO52,
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GPIO53,
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GPIO54,
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GPIO55,
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GPIO56,
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GPIO57,
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GPIO58,
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GPIO59,
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GPIO60, /* 60 */
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GPIO61,
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GPIO62,
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GPIO63,
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GPIO64,
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GPIO65,
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GPIO66,
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GPIO67,
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GPIO68,
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GPIO69,
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GPIO70, /* 70 */
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GPIO71,
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GPIO72,
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GPIO73,
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GPIO74,
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GPIO75,
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GPIO76,
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GPIO77,
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GPIO78,
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GPIO79,
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GPIO80, /* 80 */
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GPIO81,
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GPIO82,
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GPIO83,
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GPIO84,
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GPIO85,
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GPIO86,
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GPIO87,
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GPIO88,
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GPIO89,
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GPIO90, /* 90 */
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GPIO91,
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GPIO92,
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GPIO93,
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GPIO94,
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GPIO95,
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GPIO96,
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GPIO97,
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GPIO98,
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GPIO99,
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GPIO100, /* 100 */
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GPIO101,
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GPIO102,
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GPIO103,
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GPIO104,
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GPIO105,
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GPIO106,
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GPIO107,
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GPIO108,
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GPIO109,
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GPIO110, /* 110 */
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GPIO111,
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GPIO112,
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GPIO113,
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GPIO114,
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GPIO115,
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GPIO116,
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GPIO117,
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GPIO118,
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GPIO119,
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GPIO120, /* 120 */
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GPIO121,
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GPIO122,
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GPIO123,
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GPIO124,
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GPIO125,
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GPIO126,
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GPIO127,
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GPIO128,
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GPIO129,
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GPIO130, /* 130 */
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GPIO131,
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GPIO132,
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GPIO133,
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GPIO134,
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GPIO135,
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GPIO136,
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GPIO137,
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GPIO138,
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GPIO139,
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GPIO140, /* 140 */
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GPIO141,
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GPIO142,
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GPIO143,
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GPIO144,
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GPIO145,
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GPIO146,
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GPIO147,
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GPIO148,
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GPIO149,
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GPIO150, /* 150 */
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GPIO151,
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GPIO152,
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GPIO153,
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GPIO154,
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GPIO155,
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GPIO156,
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GPIO157,
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GPIO158,
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GPIO159,
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GPIO160, /* 160 */
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GPIO161,
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GPIO162,
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GPIO163,
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GPIO164,
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GPIO165,
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GPIO166,
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GPIO167,
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GPIO168,
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GPIO169,
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};
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extern int pxa3xx_pinctrl_register(struct platform_device *pdev,
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struct pxa3xx_pinmux_info *info);
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extern int pxa3xx_pinctrl_unregister(struct platform_device *pdev);
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#endif /* __PINCTRL_PXA3XX_H */
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