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ccf68e59e9
Fit blackfin uart over sport driver into common uart inftrastructure. It is based on the early platform interfaces to get the platform data early when the console is initilized. 1. Enable sport uart driver to change uart baud, data bit, stop bit at runtime. Bind the index of uart device nodes to physical index of sports. 2. Move all platform data into arch specific board files. Register and probe platform device data in both early and normal stages. 3. Console is registered in sport uart driver as well. 4. Remove 500 us block waiting in sport tx stop code by putting a dummy data into tx fifo to make sure the sport tx stops when all bytes are shifted out except for the dummy data. 5. clean up a bit and fix up coding style. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Bryan Wu <cooloney@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
62 lines
3.3 KiB
C
62 lines
3.3 KiB
C
/*
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* Blackfin On-Chip Sport Emulated UART Driver
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*
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* Copyright 2006-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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/*
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* This driver and the hardware supported are in term of EE-191 of ADI.
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* http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
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* This application note describe how to implement a UART on a Sharc DSP,
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* but this driver is implemented on Blackfin Processor.
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* Transmit Frame Sync is not used by this driver to transfer data out.
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*/
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#ifndef _BFIN_SPORT_UART_H
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#define _BFIN_SPORT_UART_H
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#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */
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#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */
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#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */
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#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */
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#define OFFSET_TX 0x10 /* Transmit Data Register */
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#define OFFSET_RX 0x18 /* Receive Data Register */
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#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */
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#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */
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#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */
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#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */
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#define OFFSET_STAT 0x30 /* Status Register */
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#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1))
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#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2))
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#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
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#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
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#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX))
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#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX))
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#define SPORT_GET_RX32(sport) bfin_read32(((sport)->port.membase + OFFSET_RX))
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#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1))
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#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2))
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#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
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#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
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#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT))
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#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
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#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
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#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
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#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
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#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v)
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#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v)
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#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
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#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
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#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
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#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
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#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
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#define SPORT_TX_FIFO_SIZE 8
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#endif /* _BFIN_SPORT_UART_H */
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