mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 02:34:01 +08:00
13fa14e185
Mimicks almost perfectly the powerpc IOMMU code, except that it doesn't have the IOMMU_PAGE_SIZE != PAGE_SIZE handling, and it also lacks the device dma mask support bits. I'll add that later as time permits, but this gets us at least back to where we were beforehand. Signed-off-by: David S. Miller <davem@davemloft.net>
490 lines
13 KiB
C
490 lines
13 KiB
C
#ifndef __SPARC64_IO_H
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#define __SPARC64_IO_H
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/page.h> /* IO address mapping routines need this */
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#include <asm/system.h>
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#include <asm/asi.h>
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/* PC crapola... */
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#define __SLOW_DOWN_IO do { } while (0)
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#define SLOW_DOWN_IO do { } while (0)
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/* BIO layer definitions. */
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extern unsigned long kern_base, kern_size;
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#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
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#define BIO_VMERGE_BOUNDARY 8192
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static inline u8 _inb(unsigned long addr)
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{
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u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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return ret;
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}
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static inline u16 _inw(unsigned long addr)
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{
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u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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return ret;
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}
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static inline u32 _inl(unsigned long addr)
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{
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u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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return ret;
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}
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static inline void _outb(u8 b, unsigned long addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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}
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static inline void _outw(u16 w, unsigned long addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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}
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static inline void _outl(u32 l, unsigned long addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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}
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#define inb(__addr) (_inb((unsigned long)(__addr)))
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#define inw(__addr) (_inw((unsigned long)(__addr)))
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#define inl(__addr) (_inl((unsigned long)(__addr)))
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#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
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#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
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#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
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#define inb_p(__addr) inb(__addr)
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#define outb_p(__b, __addr) outb(__b, __addr)
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#define inw_p(__addr) inw(__addr)
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#define outw_p(__w, __addr) outw(__w, __addr)
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#define inl_p(__addr) inl(__addr)
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#define outl_p(__l, __addr) outl(__l, __addr)
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extern void outsb(unsigned long, const void *, unsigned long);
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extern void outsw(unsigned long, const void *, unsigned long);
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extern void outsl(unsigned long, const void *, unsigned long);
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extern void insb(unsigned long, void *, unsigned long);
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extern void insw(unsigned long, void *, unsigned long);
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extern void insl(unsigned long, void *, unsigned long);
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static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
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{
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insb((unsigned long __force)port, buf, count);
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}
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static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
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{
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insw((unsigned long __force)port, buf, count);
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}
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static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
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{
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insl((unsigned long __force)port, buf, count);
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}
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static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
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{
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outsb((unsigned long __force)port, buf, count);
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}
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static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
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{
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outsw((unsigned long __force)port, buf, count);
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}
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static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
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{
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outsl((unsigned long __force)port, buf, count);
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}
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/* Memory functions, same as I/O accesses on Ultra. */
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static inline u8 _readb(const volatile void __iomem *addr)
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{ u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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return ret;
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}
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static inline u16 _readw(const volatile void __iomem *addr)
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{ u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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return ret;
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}
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static inline u32 _readl(const volatile void __iomem *addr)
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{ u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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return ret;
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}
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static inline u64 _readq(const volatile void __iomem *addr)
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{ u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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return ret;
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}
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static inline void _writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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}
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static inline void _writew(u16 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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}
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static inline void _writel(u32 l, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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}
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static inline void _writeq(u64 q, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
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}
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#define readb(__addr) _readb(__addr)
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#define readw(__addr) _readw(__addr)
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#define readl(__addr) _readl(__addr)
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#define readq(__addr) _readq(__addr)
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#define readb_relaxed(__addr) _readb(__addr)
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#define readw_relaxed(__addr) _readw(__addr)
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#define readl_relaxed(__addr) _readl(__addr)
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#define readq_relaxed(__addr) _readq(__addr)
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#define writeb(__b, __addr) _writeb(__b, __addr)
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#define writew(__w, __addr) _writew(__w, __addr)
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#define writel(__l, __addr) _writel(__l, __addr)
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#define writeq(__q, __addr) _writeq(__q, __addr)
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/* Now versions without byte-swapping. */
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static inline u8 _raw_readb(unsigned long addr)
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{
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u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline u16 _raw_readw(unsigned long addr)
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{
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u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline u32 _raw_readl(unsigned long addr)
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{
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u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline u64 _raw_readq(unsigned long addr)
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{
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u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline void _raw_writeb(u8 b, unsigned long addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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static inline void _raw_writew(u16 w, unsigned long addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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static inline void _raw_writel(u32 l, unsigned long addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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static inline void _raw_writeq(u64 q, unsigned long addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
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: /* no outputs */
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: "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr)))
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#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr)))
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#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr)))
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#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr)))
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#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
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#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
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#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
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#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
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/* Valid I/O Space regions are anywhere, because each PCI bus supported
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* can live in an arbitrary area of the physical address range.
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*/
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#define IO_SPACE_LIMIT 0xffffffffffffffffUL
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/* Now, SBUS variants, only difference from PCI is that we do
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* not use little-endian ASIs.
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*/
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static inline u8 _sbus_readb(const volatile void __iomem *addr)
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{
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u8 ret;
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__asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline u16 _sbus_readw(const volatile void __iomem *addr)
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{
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u16 ret;
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__asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline u32 _sbus_readl(const volatile void __iomem *addr)
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{
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u32 ret;
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__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline u64 _sbus_readq(const volatile void __iomem *addr)
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{
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u64 ret;
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__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
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: "=r" (ret)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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return ret;
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}
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static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
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: /* no outputs */
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: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
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: /* no outputs */
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: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
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{
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__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
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: /* no outputs */
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: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
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}
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#define sbus_readb(__addr) _sbus_readb(__addr)
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#define sbus_readw(__addr) _sbus_readw(__addr)
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#define sbus_readl(__addr) _sbus_readl(__addr)
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#define sbus_readq(__addr) _sbus_readq(__addr)
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#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
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#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
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#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
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#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
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static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
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{
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while(n--) {
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sbus_writeb(c, dst);
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dst++;
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}
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}
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#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
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static inline void
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_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
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{
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volatile void __iomem *d = dst;
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while (n--) {
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writeb(c, d);
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d++;
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}
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}
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#define memset_io(d,c,sz) _memset_io(d,c,sz)
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static inline void
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_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
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{
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char *d = dst;
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while (n--) {
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char tmp = readb(src);
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*d++ = tmp;
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src++;
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}
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}
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#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
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static inline void
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_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
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{
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const char *s = src;
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volatile void __iomem *d = dst;
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while (n--) {
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char tmp = *s++;
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writeb(tmp, d);
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d++;
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}
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}
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#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
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#define mmiowb()
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#ifdef __KERNEL__
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/* On sparc64 we have the whole physical IO address space accessible
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* using physically addressed loads and stores, so this does nothing.
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*/
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static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
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{
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return (void __iomem *)offset;
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}
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#define ioremap_nocache(X,Y) ioremap((X),(Y))
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static inline void iounmap(volatile void __iomem *addr)
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{
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}
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#define ioread8(X) readb(X)
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#define ioread16(X) readw(X)
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#define ioread32(X) readl(X)
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#define iowrite8(val,X) writeb(val,X)
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#define iowrite16(val,X) writew(val,X)
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#define iowrite32(val,X) writel(val,X)
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|
|
|
/* Create a virtual mapping cookie for an IO port range */
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extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
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extern void ioport_unmap(void __iomem *);
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|
|
|
/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
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|
struct pci_dev;
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extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
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|
|
|
/* Similarly for SBUS. */
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|
#define sbus_ioremap(__res, __offset, __size, __name) \
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|
({ unsigned long __ret; \
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|
__ret = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
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|
__ret += (unsigned long) (__offset); \
|
|
if (! request_region((__ret), (__size), (__name))) \
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|
__ret = 0UL; \
|
|
(void __iomem *) __ret; \
|
|
})
|
|
|
|
#define sbus_iounmap(__addr, __size) \
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|
release_region((unsigned long)(__addr), (__size))
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|
|
|
/*
|
|
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
|
* access
|
|
*/
|
|
#define xlate_dev_mem_ptr(p) __va(p)
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|
|
|
/*
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
*/
|
|
#define xlate_dev_kmem_ptr(p) p
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|
|
|
#endif
|
|
|
|
#endif /* !(__SPARC64_IO_H) */
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