Sergei Shtylyov 9ef5e0370d clk: renesas: r8a77970: Add TPU clock ... The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke Matsushita, it was added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>		2018-09-25 08:56:09 +02:00
..
clk-div6.c	clk: renesas: div6: Always use readl()/writel()	2018-03-21 17:34:29 +01:00
clk-div6.h	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
clk-emev2.c
clk-mstp.c	clk: renesas: mstp: Always use readl()/writel()	2018-03-21 17:34:49 +01:00
clk-r8a73a4.c	clk: renesas: r8a73a4: Always use readl()/writel()	2018-03-21 17:34:51 +01:00
clk-r8a7740.c	treewide: kzalloc() -> kcalloc()	2018-06-12 16:19:22 -07:00
clk-r8a7778.c	clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()	2016-11-02 20:44:14 +01:00
clk-r8a7779.c	treewide: kzalloc() -> kcalloc()	2018-06-12 16:19:22 -07:00
clk-rcar-gen2.c	treewide: kzalloc() -> kcalloc()	2018-06-12 16:19:22 -07:00
clk-rz.c	treewide: kzalloc() -> kcalloc()	2018-06-12 16:19:22 -07:00
clk-sh73a0.c	clk: renesas: Updates for v4.17 (take two)	2018-03-23 09:40:52 -07:00
Kconfig	clk: renesas: cpg-mssr: Add r8a774c0 support	2018-09-19 16:42:14 +02:00
Makefile	clk: renesas: cpg-mssr: Add r8a774c0 support	2018-09-19 16:42:14 +02:00
r7s9210-cpg-mssr.c	clk: renesas: cpg-mssr: Add R7S9210 support	2018-09-11 12:01:07 +02:00
r8a774a1-cpg-mssr.c	clk: renesas: cpg-mssr: Add r8a774a1 support	2018-08-27 17:00:19 +02:00
r8a774c0-cpg-mssr.c	clk: renesas: cpg-mssr: Add r8a774c0 support	2018-09-19 16:42:14 +02:00
r8a7743-cpg-mssr.c	clk: renesas: r8a7743: Add r8a7744 support	2018-09-19 16:39:45 +02:00
r8a7745-cpg-mssr.c	clk: renesas: r8a7745: Fix LB clock divider	2018-04-16 13:39:45 +02:00
r8a7790-cpg-mssr.c	clk: renesas: r8a7790: Add rwdt clock	2018-02-20 13:35:16 +01:00
r8a7791-cpg-mssr.c	clk: renesas: r8a7791/r8a7793: Fix LB clock divider	2018-04-16 13:39:47 +02:00
r8a7792-cpg-mssr.c	clk: renesas: r8a7792: Fix LB clock divider	2018-04-16 13:39:49 +02:00
r8a7794-cpg-mssr.c	clk: renesas: r8a7794: Fix LB clock divider	2018-04-16 13:39:51 +02:00
r8a7795-cpg-mssr.c	clk: renesas: r8a7795: Add OSC EXTAL predivider configuration	2018-08-27 17:00:18 +02:00
r8a7796-cpg-mssr.c	clk: renesas: r8a7796: Add OSC EXTAL predivider configuration	2018-08-27 17:00:18 +02:00
r8a77470-cpg-mssr.c	clk: renesas: cpg-mssr: Add r8a77470 support	2018-04-16 13:39:40 +02:00
r8a77965-cpg-mssr.c	clk: renesas: r8a77965: Add FDP clock	2018-08-28 11:06:11 +02:00
r8a77970-cpg-mssr.c	clk: renesas: r8a77970: Add TPU clock	2018-09-25 08:56:09 +02:00
r8a77980-cpg-mssr.c	clk: renesas: r8a77980: Add CMT clocks	2018-09-03 09:58:33 +02:00
r8a77990-cpg-mssr.c	clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment	2018-09-25 08:55:56 +02:00
r8a77995-cpg-mssr.c	clk: renesas: r8a77995: Correct RCLK handling	2018-08-27 17:00:18 +02:00
r9a06g032-clocks.c	clk: renesas: r9a06g032: Fix UART34567 clock rate	2018-09-11 11:57:25 +02:00
rcar-gen2-cpg.c	clk: renesas: rcar-gen2: Centralize quirks handling	2018-04-16 13:42:18 +02:00
rcar-gen2-cpg.h	clk: renesas: cpg-mssr: Add support to restore core clocks during resume	2017-10-20 11:15:33 +02:00
rcar-gen3-cpg.c	clk: renesas: rcar-gen3: Add support for mode pin clock selection	2018-08-27 17:00:18 +02:00
rcar-gen3-cpg.h	clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI	2018-09-03 09:58:33 +02:00
rcar-usb2-clock-sel.c	clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY	2017-08-17 09:22:23 +02:00
renesas-cpg-mssr.c	clk: renesas: cpg-mssr: Add r8a774c0 support	2018-09-19 16:42:14 +02:00
renesas-cpg-mssr.h	clk: renesas: cpg-mssr: Add r8a774c0 support	2018-09-19 16:42:14 +02:00