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95322526ef
Kernel subsystems like CPU idle and suspend to RAM require a generic mechanism to suspend a processor, save its context and put it into a quiescent state. The cpu_{suspend}/{resume} implementation provides such a framework through a kernel interface allowing to save/restore registers, flush the context to DRAM and suspend/resume to/from low-power states where processor context may be lost. The CPU suspend implementation relies on the suspend protocol registered in CPU operations to carry out a suspend request after context is saved and flushed to DRAM. The cpu_suspend interface: int cpu_suspend(unsigned long arg); allows to pass an opaque parameter that is handed over to the suspend CPU operations back-end so that it can take action according to the semantics attached to it. The arg parameter allows suspend to RAM and CPU idle drivers to communicate to suspend protocol back-ends; it requires standardization so that the interface can be reused seamlessly across systems, paving the way for generic drivers. Context memory is allocated on the stack, whose address is stashed in a per-cpu variable to keep track of it and passed to core functions that save/restore the registers required by the architecture. Even though, upon successful execution, the cpu_suspend function shuts down the suspending processor, the warm boot resume mechanism, based on the cpu_resume function, makes the resume path operate as a cpu_suspend function return, so that cpu_suspend can be treated as a C function by the caller, which simplifies coding the PM drivers that rely on the cpu_suspend API. Upon context save, the minimal amount of memory is flushed to DRAM so that it can be retrieved when the MMU is off and caches are not searched. The suspend CPU operation, depending on the required operations (eg CPU vs Cluster shutdown) is in charge of flushing the cache hierarchy either implicitly (by calling firmware implementations like PSCI) or explicitly by executing the required cache maintainance functions. Debug exceptions are disabled during cpu_{suspend}/{resume} operations so that debug registers can be saved and restored properly preventing preemption from debug agents enabled in the kernel. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
185 lines
5.2 KiB
ArmAsm
185 lines
5.2 KiB
ArmAsm
#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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.text
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/*
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* Implementation of MPIDR_EL1 hash algorithm through shifting
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* and OR'ing.
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*
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* @dst: register containing hash result
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* @rs0: register containing affinity level 0 bit shift
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* @rs1: register containing affinity level 1 bit shift
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* @rs2: register containing affinity level 2 bit shift
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* @rs3: register containing affinity level 3 bit shift
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* @mpidr: register containing MPIDR_EL1 value
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* @mask: register containing MPIDR mask
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*
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* Pseudo C-code:
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*
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*u32 dst;
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*
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*compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
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* u32 aff0, aff1, aff2, aff3;
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* u64 mpidr_masked = mpidr & mask;
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* aff0 = mpidr_masked & 0xff;
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* aff1 = mpidr_masked & 0xff00;
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* aff2 = mpidr_masked & 0xff0000;
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* aff2 = mpidr_masked & 0xff00000000;
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* dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3);
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*}
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* Input registers: rs0, rs1, rs2, rs3, mpidr, mask
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* Output register: dst
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* Note: input and output registers must be disjoint register sets
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(eg: a macro instance with mpidr = x1 and dst = x1 is invalid)
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*/
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.macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
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and \mpidr, \mpidr, \mask // mask out MPIDR bits
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and \dst, \mpidr, #0xff // mask=aff0
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lsr \dst ,\dst, \rs0 // dst=aff0>>rs0
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and \mask, \mpidr, #0xff00 // mask = aff1
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lsr \mask ,\mask, \rs1
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orr \dst, \dst, \mask // dst|=(aff1>>rs1)
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and \mask, \mpidr, #0xff0000 // mask = aff2
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lsr \mask ,\mask, \rs2
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orr \dst, \dst, \mask // dst|=(aff2>>rs2)
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and \mask, \mpidr, #0xff00000000 // mask = aff3
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lsr \mask ,\mask, \rs3
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orr \dst, \dst, \mask // dst|=(aff3>>rs3)
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.endm
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/*
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* Save CPU state for a suspend. This saves callee registers, and allocates
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* space on the kernel stack to save the CPU specific registers + some
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* other data for resume.
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*
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* x0 = suspend finisher argument
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*/
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ENTRY(__cpu_suspend)
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stp x29, lr, [sp, #-96]!
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stp x19, x20, [sp,#16]
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stp x21, x22, [sp,#32]
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stp x23, x24, [sp,#48]
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stp x25, x26, [sp,#64]
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stp x27, x28, [sp,#80]
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mov x2, sp
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sub sp, sp, #CPU_SUSPEND_SZ // allocate cpu_suspend_ctx
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mov x1, sp
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/*
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* x1 now points to struct cpu_suspend_ctx allocated on the stack
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*/
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str x2, [x1, #CPU_CTX_SP]
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ldr x2, =sleep_save_sp
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ldr x2, [x2, #SLEEP_SAVE_SP_VIRT]
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#ifdef CONFIG_SMP
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mrs x7, mpidr_el1
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ldr x9, =mpidr_hash
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ldr x10, [x9, #MPIDR_HASH_MASK]
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/*
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* Following code relies on the struct mpidr_hash
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* members size.
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*/
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ldp w3, w4, [x9, #MPIDR_HASH_SHIFTS]
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ldp w5, w6, [x9, #(MPIDR_HASH_SHIFTS + 8)]
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compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10
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add x2, x2, x8, lsl #3
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#endif
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bl __cpu_suspend_finisher
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/*
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* Never gets here, unless suspend fails.
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* Successful cpu_suspend should return from cpu_resume, returning
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* through this code path is considered an error
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* If the return value is set to 0 force x0 = -EOPNOTSUPP
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* to make sure a proper error condition is propagated
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*/
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cmp x0, #0
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mov x3, #-EOPNOTSUPP
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csel x0, x3, x0, eq
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add sp, sp, #CPU_SUSPEND_SZ // rewind stack pointer
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ldp x19, x20, [sp, #16]
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ldp x21, x22, [sp, #32]
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ldp x23, x24, [sp, #48]
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ldp x25, x26, [sp, #64]
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ldp x27, x28, [sp, #80]
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ldp x29, lr, [sp], #96
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ret
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ENDPROC(__cpu_suspend)
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.ltorg
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/*
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* x0 must contain the sctlr value retrieved from restored context
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*/
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ENTRY(cpu_resume_mmu)
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ldr x3, =cpu_resume_after_mmu
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msr sctlr_el1, x0 // restore sctlr_el1
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isb
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br x3 // global jump to virtual address
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ENDPROC(cpu_resume_mmu)
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cpu_resume_after_mmu:
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mov x0, #0 // return zero on success
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ldp x19, x20, [sp, #16]
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ldp x21, x22, [sp, #32]
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ldp x23, x24, [sp, #48]
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ldp x25, x26, [sp, #64]
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ldp x27, x28, [sp, #80]
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ldp x29, lr, [sp], #96
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ret
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ENDPROC(cpu_resume_after_mmu)
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.data
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ENTRY(cpu_resume)
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bl el2_setup // if in EL2 drop to EL1 cleanly
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#ifdef CONFIG_SMP
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mrs x1, mpidr_el1
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adr x4, mpidr_hash_ptr
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ldr x5, [x4]
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add x8, x4, x5 // x8 = struct mpidr_hash phys address
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/* retrieve mpidr_hash members to compute the hash */
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ldr x2, [x8, #MPIDR_HASH_MASK]
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ldp w3, w4, [x8, #MPIDR_HASH_SHIFTS]
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ldp w5, w6, [x8, #(MPIDR_HASH_SHIFTS + 8)]
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compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2
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/* x7 contains hash index, let's use it to grab context pointer */
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#else
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mov x7, xzr
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#endif
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adr x0, sleep_save_sp
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ldr x0, [x0, #SLEEP_SAVE_SP_PHYS]
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ldr x0, [x0, x7, lsl #3]
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/* load sp from context */
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ldr x2, [x0, #CPU_CTX_SP]
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adr x1, sleep_idmap_phys
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/* load physical address of identity map page table in x1 */
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ldr x1, [x1]
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mov sp, x2
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/*
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* cpu_do_resume expects x0 to contain context physical address
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* pointer and x1 to contain physical address of 1:1 page tables
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*/
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bl cpu_do_resume // PC relative jump, MMU off
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b cpu_resume_mmu // Resume MMU, never returns
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ENDPROC(cpu_resume)
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.align 3
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mpidr_hash_ptr:
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/*
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* offset of mpidr_hash symbol from current location
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* used to obtain run-time mpidr_hash address with MMU off
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*/
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.quad mpidr_hash - .
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/*
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* physical address of identity mapped page tables
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*/
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.type sleep_idmap_phys, #object
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ENTRY(sleep_idmap_phys)
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.quad 0
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/*
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* struct sleep_save_sp {
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* phys_addr_t *save_ptr_stash;
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* phys_addr_t save_ptr_stash_phys;
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* };
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*/
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.type sleep_save_sp, #object
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ENTRY(sleep_save_sp)
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.space SLEEP_SAVE_SP_SZ // struct sleep_save_sp
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