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b547631fc6
Allow access to the 32bit register file through the usual API. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
169 lines
4.7 KiB
C
169 lines
4.7 KiB
C
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/kvm/emulate.c:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/mm.h>
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/ptrace.h>
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#define VCPU_NR_MODES 6
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#define REG_OFFSET(_reg) \
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(offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long))
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#define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
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static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][16] = {
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/* USR Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
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REG_OFFSET(pc)
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},
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/* FIQ Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7),
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REG_OFFSET(compat_r8_fiq), /* r8 */
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REG_OFFSET(compat_r9_fiq), /* r9 */
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REG_OFFSET(compat_r10_fiq), /* r10 */
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REG_OFFSET(compat_r11_fiq), /* r11 */
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REG_OFFSET(compat_r12_fiq), /* r12 */
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REG_OFFSET(compat_sp_fiq), /* r13 */
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REG_OFFSET(compat_lr_fiq), /* r14 */
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REG_OFFSET(pc)
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},
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/* IRQ Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_irq), /* r13 */
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REG_OFFSET(compat_lr_irq), /* r14 */
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REG_OFFSET(pc)
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},
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/* SVC Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_svc), /* r13 */
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REG_OFFSET(compat_lr_svc), /* r14 */
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REG_OFFSET(pc)
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},
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/* ABT Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_abt), /* r13 */
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REG_OFFSET(compat_lr_abt), /* r14 */
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REG_OFFSET(pc)
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},
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/* UND Registers */
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{
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USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
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USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
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USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
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USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
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USR_REG_OFFSET(12),
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REG_OFFSET(compat_sp_und), /* r13 */
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REG_OFFSET(compat_lr_und), /* r14 */
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REG_OFFSET(pc)
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},
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};
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/*
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* Return a pointer to the register number valid in the current mode of
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* the virtual CPU.
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*/
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num)
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{
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unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs.regs;
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unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
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switch (mode) {
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case COMPAT_PSR_MODE_USR ... COMPAT_PSR_MODE_SVC:
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mode &= ~PSR_MODE32_BIT; /* 0 ... 3 */
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break;
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case COMPAT_PSR_MODE_ABT:
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mode = 4;
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break;
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case COMPAT_PSR_MODE_UND:
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mode = 5;
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break;
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case COMPAT_PSR_MODE_SYS:
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mode = 0; /* SYS maps to USR */
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break;
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default:
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BUG();
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}
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return reg_array + vcpu_reg_offsets[mode][reg_num];
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}
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/*
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* Return the SPSR for the current mode of the virtual CPU.
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*/
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unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu)
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{
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unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
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switch (mode) {
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case COMPAT_PSR_MODE_SVC:
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mode = KVM_SPSR_SVC;
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break;
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case COMPAT_PSR_MODE_ABT:
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mode = KVM_SPSR_ABT;
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break;
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case COMPAT_PSR_MODE_UND:
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mode = KVM_SPSR_UND;
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break;
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case COMPAT_PSR_MODE_IRQ:
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mode = KVM_SPSR_IRQ;
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break;
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case COMPAT_PSR_MODE_FIQ:
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mode = KVM_SPSR_FIQ;
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break;
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default:
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BUG();
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}
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return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[mode];
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}
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