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171699f763
Add support for the new clflushopt instruction. This instruction was announced in the document "Intel Architecture Instruction Set Extensions Programming Reference" with Ref # 319433-018. http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf [ hpa: changed the feature flag to simply X86_FEATURE_CLFLUSHOPT - if that is what we want to report in /proc/cpuinfo anyway... ] Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Link: http://lkml.kernel.org/r/1393441612-19729-2-git-send-email-ross.zwisler@linux.intel.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
208 lines
4.1 KiB
C
208 lines
4.1 KiB
C
#ifndef _ASM_X86_SPECIAL_INSNS_H
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#define _ASM_X86_SPECIAL_INSNS_H
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#ifdef __KERNEL__
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static inline void native_clts(void)
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{
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asm volatile("clts");
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}
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/*
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* Volatile isn't enough to prevent the compiler from reordering the
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* read/write functions for the control registers and messing everything up.
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* A memory clobber would solve the problem, but would prevent reordering of
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* all loads stores around it, which can hurt performance. Solution is to
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* use a variable and mimic reads and writes to it to enforce serialization
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*/
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extern unsigned long __force_order;
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static inline unsigned long native_read_cr0(void)
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{
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unsigned long val;
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asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr0(unsigned long val)
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{
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asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr2(unsigned long val)
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{
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asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr3(void)
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{
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unsigned long val;
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asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr3(unsigned long val)
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{
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asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long native_read_cr4_safe(void)
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{
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unsigned long val;
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/* This could fault if %cr4 does not exist. In x86_64, a cr4 always
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* exists, so it will never fail. */
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#ifdef CONFIG_X86_32
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asm volatile("1: mov %%cr4, %0\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b)
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: "=r" (val), "=m" (__force_order) : "0" (0));
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#else
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val = native_read_cr4();
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#endif
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return val;
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}
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static inline void native_write_cr4(unsigned long val)
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{
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asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
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}
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#ifdef CONFIG_X86_64
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static inline unsigned long native_read_cr8(void)
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{
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unsigned long cr8;
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asm volatile("movq %%cr8,%0" : "=r" (cr8));
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return cr8;
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}
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static inline void native_write_cr8(unsigned long val)
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{
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asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
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}
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#endif
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static inline void native_wbinvd(void)
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{
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asm volatile("wbinvd": : :"memory");
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}
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extern asmlinkage void native_load_gs_index(unsigned);
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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static inline unsigned long read_cr0(void)
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{
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return native_read_cr0();
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}
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static inline void write_cr0(unsigned long x)
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{
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native_write_cr0(x);
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}
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static inline unsigned long read_cr2(void)
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{
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return native_read_cr2();
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}
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static inline void write_cr2(unsigned long x)
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{
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native_write_cr2(x);
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}
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static inline unsigned long read_cr3(void)
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{
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return native_read_cr3();
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}
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static inline void write_cr3(unsigned long x)
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{
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native_write_cr3(x);
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}
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static inline unsigned long read_cr4(void)
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{
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return native_read_cr4();
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}
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static inline unsigned long read_cr4_safe(void)
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{
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return native_read_cr4_safe();
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}
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static inline void write_cr4(unsigned long x)
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{
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native_write_cr4(x);
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}
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static inline void wbinvd(void)
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{
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native_wbinvd();
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}
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#ifdef CONFIG_X86_64
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static inline unsigned long read_cr8(void)
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{
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return native_read_cr8();
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}
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static inline void write_cr8(unsigned long x)
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{
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native_write_cr8(x);
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}
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static inline void load_gs_index(unsigned selector)
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{
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native_load_gs_index(selector);
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}
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#endif
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/* Clear the 'TS' bit */
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static inline void clts(void)
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{
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native_clts();
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}
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#endif/* CONFIG_PARAVIRT */
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#define stts() write_cr0(read_cr0() | X86_CR0_TS)
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static inline void clflush(volatile void *__p)
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{
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asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
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}
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static inline void clflushopt(volatile void *__p)
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{
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alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
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".byte 0x66; clflush %P0",
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X86_FEATURE_CLFLUSHOPT,
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"+m" (*(volatile char __force *)__p));
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}
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#define nop() asm volatile ("nop")
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_SPECIAL_INSNS_H */
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