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825f4e0271
A quite large set of SoC updates this cycle. In no particular order: - Multi-cluster power management for Samsung Exynos, adding support for big.LITTLE CPU switching on EXYNOS5 - SMP support for Marvell Armada 375 and 38x - SMP rework on Allwinner A31 - Xilinx Zynq support for SOC_BUS, big endian - Marvell orion5x platform cleanup, modernizing the implementation and moving to DT. - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so that their platform can be enabled in the same kernel binary as most of the other v7 platforms in the tree. \o/ The work isn't quite complete, there's some driver fixes still needed, but the basics now work. New SoC support added: - Freescale i.MX6SX - LSI Axxia AXM55xx SoCs - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800 - STi STIH407 Plus a large set of various smaller updates for different platforms. I'm probably missing some important one here. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTjOKWAAoJEIwa5zzehBx36aEP/2vTD7x9FC59FACNHJ8iO7aw 0ebTgBBjI1Np6X18O+M7URbxV5TaBgwpUm/NDN86p03MpQ2eOXr8r47qVxe/HhZs AdlTvzgE6QwxcVL/HeCKKUEN3BPH74+TZgFl9I5aSzNjpR39xETeK1aWP/ZiAl/q /lGRZAQ59+c7Ung00Hg0g2YDxH9WFpK50Nj90ROnyjKSFkhIYngXYVpZB3maOypq Pgib/U8IraKZ52oGJw3yinSoORr7FdcUdAGWGTz/lQdNL/jYDfQ6GkRW2oblWXdt 3Xvj9UW6NmkbMICucMvFuuW1nXAgutZuTp9w7mBxsiUlYepxPv/DXM6yiI1WGlEb BeVOmOreNeN2nT6avv/uUhk3Osq63Jn9x8cz5y+7/lgWQwllh3/c+G01RotvgJEQ vpQq5ps9fMxIAMaNP6N/YqMJI1IOrBj0iXxaZEDw3VYM/k4lSvtb3VXP9c/rqApu U4i6hpSIGzrraU4NrjndYPndcLeNOVZbByETQKosZXuCo6G1sb7FstNSkzI9vSo8 O/pujIVUfYyBW82GzZGDw+aa7DWA29FPeUQ3p+sj5MSCg051xXT8h6QwqMo2K/zY 5ATs/qo6w7zH/Ou9rtHTRynCIb0GQJThDSlWtuXFedUF9quEltS+TDz/2o+dWtGJ yBFGKDRuBB20D36w9xqg =6LYI -----END PGP SIGNATURE----- Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next Pull part one of ARM SoC updates from Olof Johansson: "A quite large set of SoC updates this cycle. In no particular order: - Multi-cluster power management for Samsung Exynos, adding support for big.LITTLE CPU switching on EXYNOS5 - SMP support for Marvell Armada 375 and 38x - SMP rework on Allwinner A31 - Xilinx Zynq support for SOC_BUS, big endian - Marvell orion5x platform cleanup, modernizing the implementation and moving to DT. - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so that their platform can be enabled in the same kernel binary as most of the other v7 platforms in the tree. \o/ The work isn't quite complete, there's some driver fixes still needed, but the basics now work. New SoC support added: - Freescale i.MX6SX - LSI Axxia AXM55xx SoCs - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800 - STi STIH407 plus a large set of various smaller updates for different platforms. I'm probably missing some important one here" * tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits) ARM: exynos: don't run exynos4 l2x0 setup on other platforms ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug ARM: EXYNOS: mcpm rename the power_down_finish ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC ARM: EXYNOS: Enable multi-platform build support ARM: EXYNOS: Consolidate Kconfig entries ARM: EXYNOS: Add support for EXYNOS5410 SoC ARM: EXYNOS: Support secondary CPU boot of Exynos3250 ARM: EXYNOS: Add Exynos3250 SoC ID ARM: EXYNOS: Add 5800 SoC support ARM: EXYNOS: initial board support for exynos5260 SoC clk: exynos5410: register clocks using common clock framework ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084 ARM: sunxi: allow building without reset controller Documentation: devicetree: arm: sort enable-method entries ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks ARM: dts: axxia: Add reset controller power: reset: Add Axxia system reset driver ARM: axxia: Adding defconfig for AXM55xx ...
450 lines
13 KiB
Plaintext
450 lines
13 KiB
Plaintext
Device Tree Clock bindings for arch-at91
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"atmel,at91sam9x5-sckc":
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at91 SCKC (Slow Clock Controller)
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This node contains the slow clock definitions.
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"atmel,at91sam9x5-clk-slow-osc":
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at91 slow oscillator
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"atmel,at91sam9x5-clk-slow-rc-osc":
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at91 internal slow RC oscillator
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"atmel,at91rm9200-pmc" or
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"atmel,at91sam9g45-pmc" or
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"atmel,at91sam9n12-pmc" or
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"atmel,at91sam9x5-pmc" or
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"atmel,sama5d3-pmc":
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at91 PMC (Power Management Controller)
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All at91 specific clocks (clocks defined below) must be child
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node of the PMC node.
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"atmel,at91sam9x5-clk-slow" (under sckc node)
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or
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"atmel,at91sam9260-clk-slow" (under pmc node):
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at91 slow clk
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"atmel,at91rm9200-clk-main-osc"
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"atmel,at91sam9x5-clk-main-rc-osc"
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at91 main clk sources
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"atmel,at91sam9x5-clk-main"
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"atmel,at91rm9200-clk-main":
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at91 main clock
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"atmel,at91rm9200-clk-master" or
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"atmel,at91sam9x5-clk-master":
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at91 master clock
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"atmel,at91sam9x5-clk-peripheral" or
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"atmel,at91rm9200-clk-peripheral":
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at91 peripheral clocks
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"atmel,at91rm9200-clk-pll" or
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"atmel,at91sam9g45-clk-pll" or
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"atmel,at91sam9g20-clk-pllb" or
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"atmel,sama5d3-clk-pll":
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at91 pll clocks
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"atmel,at91sam9x5-clk-plldiv":
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at91 plla divisor
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"atmel,at91rm9200-clk-programmable" or
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"atmel,at91sam9g45-clk-programmable" or
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"atmel,at91sam9x5-clk-programmable":
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at91 programmable clocks
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"atmel,at91sam9x5-clk-smd":
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at91 SMD (Soft Modem) clock
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"atmel,at91rm9200-clk-system":
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at91 system clocks
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"atmel,at91rm9200-clk-usb" or
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"atmel,at91sam9x5-clk-usb" or
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"atmel,at91sam9n12-clk-usb":
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at91 usb clock
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"atmel,at91sam9x5-clk-utmi":
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at91 utmi clock
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Required properties for SCKC node:
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- reg : defines the IO memory reserved for the SCKC.
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- #size-cells : shall be 0 (reg is used to encode clk id).
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- #address-cells : shall be 1 (reg is used to encode clk id).
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For example:
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sckc: sckc@fffffe50 {
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compatible = "atmel,sama5d3-pmc";
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reg = <0xfffffe50 0x4>
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#size-cells = <0>;
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#address-cells = <1>;
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/* put at91 slow clocks here */
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};
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Required properties for internal slow RC oscillator:
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- #clock-cells : from common clock binding; shall be set to 0.
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- clock-frequency : define the internal RC oscillator frequency.
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Optional properties:
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- clock-accuracy : define the internal RC oscillator accuracy.
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For example:
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slow_rc_osc: slow_rc_osc {
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compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
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clock-frequency = <32768>;
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clock-accuracy = <50000000>;
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};
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Required properties for slow oscillator:
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall encode the main osc source clk sources (see atmel datasheet).
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Optional properties:
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- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
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provided on XIN.
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For example:
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slow_osc: slow_osc {
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compatible = "atmel,at91rm9200-clk-slow-osc";
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#clock-cells = <0>;
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clocks = <&slow_xtal>;
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};
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Required properties for slow clock:
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall encode the slow clk sources (see atmel datasheet).
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For example:
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clk32k: slck {
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compatible = "atmel,at91sam9x5-clk-slow";
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#clock-cells = <0>;
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clocks = <&slow_rc_osc &slow_osc>;
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};
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Required properties for PMC node:
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- reg : defines the IO memory reserved for the PMC.
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- #size-cells : shall be 0 (reg is used to encode clk id).
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- #address-cells : shall be 1 (reg is used to encode clk id).
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- interrupts : shall be set to PMC interrupt line.
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- interrupt-controller : tell that the PMC is an interrupt controller.
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- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
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and reflect the bit position in the PMC_ER/DR/SR registers.
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You can use the dt macros defined in dt-bindings/clock/at91.h.
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0 (AT91_PMC_MOSCS) -> main oscillator ready
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1 (AT91_PMC_LOCKA) -> PLL A ready
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2 (AT91_PMC_LOCKB) -> PLL B ready
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3 (AT91_PMC_MCKRDY) -> master clock ready
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6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
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8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
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16 (AT91_PMC_MOSCSELS) -> main oscillator selected
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17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
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18 (AT91_PMC_CFDEV) -> clock failure detected
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For example:
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pmc: pmc@fffffc00 {
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compatible = "atmel,sama5d3-pmc";
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interrupts = <1 4 7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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#size-cells = <0>;
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#address-cells = <1>;
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/* put at91 clocks here */
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};
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Required properties for main clock internal RC oscillator:
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- interrupt-parent : must reference the PMC node.
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- interrupts : shall be set to "<0>".
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- clock-frequency : define the internal RC oscillator frequency.
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Optional properties:
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- clock-accuracy : define the internal RC oscillator accuracy.
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For example:
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main_rc_osc: main_rc_osc {
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compatible = "atmel,at91sam9x5-clk-main-rc-osc";
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interrupt-parent = <&pmc>;
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interrupts = <0>;
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clock-frequency = <12000000>;
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clock-accuracy = <50000000>;
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};
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Required properties for main clock oscillator:
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- interrupt-parent : must reference the PMC node.
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- interrupts : shall be set to "<0>".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall encode the main osc source clk sources (see atmel datasheet).
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Optional properties:
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- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
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on XIN.
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clock signal is directly provided on XIN pin.
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For example:
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main_osc: main_osc {
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compatible = "atmel,at91rm9200-clk-main-osc";
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interrupt-parent = <&pmc>;
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interrupts = <0>;
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#clock-cells = <0>;
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clocks = <&main_xtal>;
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};
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Required properties for main clock:
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- interrupt-parent : must reference the PMC node.
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- interrupts : shall be set to "<0>".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall encode the main clk sources (see atmel datasheet).
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For example:
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main: mainck {
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compatible = "atmel,at91sam9x5-clk-main";
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interrupt-parent = <&pmc>;
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interrupts = <0>;
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#clock-cells = <0>;
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clocks = <&main_rc_osc &main_osc>;
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};
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Required properties for master clock:
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- interrupt-parent : must reference the PMC node.
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- interrupts : shall be set to "<3>".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall be the master clock sources (see atmel datasheet) phandles.
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e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
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- atmel,clk-output-range : minimum and maximum clock frequency (two u32
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fields).
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e.g. output = <0 133000000>; <=> 0 to 133MHz.
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- atmel,clk-divisors : master clock divisors table (four u32 fields).
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0 <=> reserved value.
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e.g. divisors = <1 2 4 6>;
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- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
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PRES field as CLOCK_DIV3 (e.g sam9x5).
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For example:
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mck: mck {
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compatible = "atmel,at91rm9200-clk-master";
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interrupt-parent = <&pmc>;
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interrupts = <3>;
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#clock-cells = <0>;
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atmel,clk-output-range = <0 133000000>;
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atmel,clk-divisors = <1 2 4 0>;
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};
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Required properties for peripheral clocks:
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- #size-cells : shall be 0 (reg is used to encode clk id).
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- #address-cells : shall be 1 (reg is used to encode clk id).
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- clocks : shall be the master clock phandle.
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e.g. clocks = <&mck>;
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- name: device tree node describing a specific system clock.
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* #clock-cells : from common clock binding; shall be set to 0.
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* reg: peripheral id. See Atmel's datasheets to get a full
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list of peripheral ids.
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* atmel,clk-output-range : minimum and maximum clock frequency
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(two u32 fields). Only valid on at91sam9x5-clk-peripheral
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compatible IPs.
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For example:
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periph: periphck {
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compatible = "atmel,at91sam9x5-clk-peripheral";
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#size-cells = <0>;
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#address-cells = <1>;
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clocks = <&mck>;
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ssc0_clk {
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#clock-cells = <0>;
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reg = <2>;
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atmel,clk-output-range = <0 133000000>;
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};
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usart0_clk {
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#clock-cells = <0>;
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reg = <3>;
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atmel,clk-output-range = <0 66000000>;
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};
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};
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Required properties for pll clocks:
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- interrupt-parent : must reference the PMC node.
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- interrupts : shall be set to "<1>".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall be the main clock phandle.
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- reg : pll id.
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0 -> PLL A
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1 -> PLL B
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- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
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fields).
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e.g. input = <1 32000000>; <=> 1 to 32MHz.
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- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
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range description. Sould be set to 2, 3
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or 4.
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* 1st and 2nd cells represent the frequency range (min-max).
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* 3rd cell is optional and represents the OUT field value for the given
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range.
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* 4th cell is optional and represents the ICPLL field (PLLICPR
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register)
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- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
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depending on #atmel,pll-output-range-cells
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property value.
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For example:
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plla: pllack {
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compatible = "atmel,at91sam9g45-clk-pll";
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interrupt-parent = <&pmc>;
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interrupts = <1>;
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#clock-cells = <0>;
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clocks = <&main>;
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reg = <0>;
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atmel,clk-input-range = <2000000 32000000>;
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#atmel,pll-clk-output-range-cells = <4>;
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atmel,pll-clk-output-ranges = <74500000 800000000 0 0
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69500000 750000000 1 0
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64500000 700000000 2 0
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59500000 650000000 3 0
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54500000 600000000 0 1
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49500000 550000000 1 1
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44500000 500000000 2 1
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40000000 450000000 3 1>;
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};
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Required properties for plldiv clocks (plldiv = pll / 2):
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall be the plla clock phandle.
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The pll divisor is equal to 2 and cannot be changed.
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For example:
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plladiv: plladivck {
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compatible = "atmel,at91sam9x5-clk-plldiv";
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#clock-cells = <0>;
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clocks = <&plla>;
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};
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Required properties for programmable clocks:
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- interrupt-parent : must reference the PMC node.
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- #size-cells : shall be 0 (reg is used to encode clk id).
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- #address-cells : shall be 1 (reg is used to encode clk id).
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- clocks : shall be the programmable clock source phandles.
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e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
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- name: device tree node describing a specific prog clock.
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* #clock-cells : from common clock binding; shall be set to 0.
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* reg : programmable clock id (register offset from PCKx
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register).
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* interrupts : shall be set to "<(8 + id)>".
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For example:
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prog: progck {
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compatible = "atmel,at91sam9g45-clk-programmable";
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#size-cells = <0>;
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#address-cells = <1>;
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interrupt-parent = <&pmc>;
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clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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prog0 {
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#clock-cells = <0>;
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reg = <0>;
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interrupts = <8>;
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};
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prog1 {
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#clock-cells = <0>;
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reg = <1>;
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interrupts = <9>;
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};
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};
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Required properties for smd clock:
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : shall be the smd clock source phandles.
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e.g. clocks = <&plladiv>, <&utmi>;
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For example:
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smd: smdck {
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compatible = "atmel,at91sam9x5-clk-smd";
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#clock-cells = <0>;
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clocks = <&plladiv>, <&utmi>;
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};
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Required properties for system clocks:
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- #size-cells : shall be 0 (reg is used to encode clk id).
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- #address-cells : shall be 1 (reg is used to encode clk id).
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- name: device tree node describing a specific system clock.
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* #clock-cells : from common clock binding; shall be set to 0.
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* reg: system clock id (bit position in SCER/SCDR/SCSR registers).
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See Atmel's datasheet to get a full list of system clock ids.
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For example:
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system: systemck {
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compatible = "atmel,at91rm9200-clk-system";
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#address-cells = <1>;
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#size-cells = <0>;
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ddrck {
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#clock-cells = <0>;
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reg = <2>;
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clocks = <&mck>;
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};
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uhpck {
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#clock-cells = <0>;
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reg = <6>;
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|
clocks = <&usb>;
|
|
};
|
|
|
|
udpck {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
clocks = <&usb>;
|
|
};
|
|
};
|
|
|
|
|
|
Required properties for usb clock:
|
|
- #clock-cells : from common clock binding; shall be set to 0.
|
|
- clocks : shall be the smd clock source phandles.
|
|
e.g. clocks = <&pllb>;
|
|
- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
|
|
usb clock divisor table.
|
|
e.g. divisors = <1 2 4 0>;
|
|
|
|
For example:
|
|
usb: usbck {
|
|
compatible = "atmel,at91sam9x5-clk-usb";
|
|
#clock-cells = <0>;
|
|
clocks = <&plladiv>, <&utmi>;
|
|
};
|
|
|
|
usb: usbck {
|
|
compatible = "atmel,at91rm9200-clk-usb";
|
|
#clock-cells = <0>;
|
|
clocks = <&pllb>;
|
|
atmel,clk-divisors = <1 2 4 0>;
|
|
};
|
|
|
|
|
|
Required properties for utmi clock:
|
|
- interrupt-parent : must reference the PMC node.
|
|
- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
|
|
- #clock-cells : from common clock binding; shall be set to 0.
|
|
- clocks : shall be the main clock source phandle.
|
|
|
|
For example:
|
|
utmi: utmick {
|
|
compatible = "atmel,at91sam9x5-clk-utmi";
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
|
|
#clock-cells = <0>;
|
|
clocks = <&main>;
|
|
};
|