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70db8a6273
Enable hardware gate control for all dpll MX and X2 postdividers. This requires the allow_idle/deny_idle functions to be populated for all clock nodes (mx/x2 post dividers) in clkops. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
85 lines
1.8 KiB
C
85 lines
1.8 KiB
C
/*
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* OMAP4-specific DPLL control functions
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Rajendra Nayak
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "cm-regbits-44xx.h"
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/* Supported only on OMAP4 */
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int omap4_dpllmx_gatectrl_read(struct clk *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
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return -EINVAL;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = __raw_readl(clk->clksel_reg);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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void omap4_dpllmx_allow_gatectrl(struct clk *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
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return;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = __raw_readl(clk->clksel_reg);
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/* Clear the bit to allow gatectrl */
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v &= ~mask;
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__raw_writel(v, clk->clksel_reg);
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}
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void omap4_dpllmx_deny_gatectrl(struct clk *clk)
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{
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u32 v;
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u32 mask;
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if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
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return;
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mask = clk->flags & CLOCK_CLKOUTX2 ?
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = __raw_readl(clk->clksel_reg);
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/* Set the bit to deny gatectrl */
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v |= mask;
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__raw_writel(v, clk->clksel_reg);
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}
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const struct clkops clkops_omap4_dpllmx_ops = {
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.allow_idle = omap4_dpllmx_allow_gatectrl,
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.deny_idle = omap4_dpllmx_deny_gatectrl,
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};
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