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0bf8fa04e8
The S3C_GPIO_PULL_UP macro value incorrectly maps to a reserved setting of GPIO pull up/down registers on Exynos4 platform. Fix this incorrect mapping by adding wrappers to the s3c_gpio_setpull_updown and s3c_gpio_getpull_updown functions. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
387 lines
7.8 KiB
C
387 lines
7.8 KiB
C
/* linux/arch/arm/mach-exynos4/gpiolib.c
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/map.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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int s3c_gpio_setpull_exynos4(struct s3c_gpio_chip *chip,
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unsigned int off, s3c_gpio_pull_t pull)
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{
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if (pull == S3C_GPIO_PULL_UP)
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pull = 3;
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return s3c_gpio_setpull_updown(chip, off, pull);
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}
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s3c_gpio_pull_t s3c_gpio_getpull_exynos4(struct s3c_gpio_chip *chip,
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unsigned int off)
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{
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s3c_gpio_pull_t pull;
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pull = s3c_gpio_getpull_updown(chip, off);
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if (pull == 3)
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pull = S3C_GPIO_PULL_UP;
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return pull;
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}
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static struct s3c_gpio_cfg gpio_cfg = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_exynos4,
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.get_pull = s3c_gpio_getpull_exynos4,
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};
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static struct s3c_gpio_cfg gpio_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_exynos4,
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.get_pull = s3c_gpio_getpull_exynos4,
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};
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/*
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* Following are the gpio banks in v310.
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*
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* The 'config' member when left to NULL, is initialized to the default
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* structure gpio_cfg in the init function below.
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*
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* The 'base' member is also initialized in the init function below.
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* Note: The initialization of 'base' member of s3c_gpio_chip structure
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* uses the above macro and depends on the banks being listed in order here.
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*/
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static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
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{
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.chip = {
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.base = EXYNOS4_GPA0(0),
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.ngpio = EXYNOS4_GPIO_A0_NR,
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.label = "GPA0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPA1(0),
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.ngpio = EXYNOS4_GPIO_A1_NR,
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.label = "GPA1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPB(0),
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.ngpio = EXYNOS4_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPC0(0),
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.ngpio = EXYNOS4_GPIO_C0_NR,
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.label = "GPC0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPC1(0),
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.ngpio = EXYNOS4_GPIO_C1_NR,
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.label = "GPC1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPD0(0),
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.ngpio = EXYNOS4_GPIO_D0_NR,
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.label = "GPD0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPD1(0),
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.ngpio = EXYNOS4_GPIO_D1_NR,
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.label = "GPD1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPE0(0),
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.ngpio = EXYNOS4_GPIO_E0_NR,
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.label = "GPE0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPE1(0),
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.ngpio = EXYNOS4_GPIO_E1_NR,
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.label = "GPE1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPE2(0),
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.ngpio = EXYNOS4_GPIO_E2_NR,
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.label = "GPE2",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPE3(0),
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.ngpio = EXYNOS4_GPIO_E3_NR,
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.label = "GPE3",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPE4(0),
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.ngpio = EXYNOS4_GPIO_E4_NR,
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.label = "GPE4",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPF0(0),
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.ngpio = EXYNOS4_GPIO_F0_NR,
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.label = "GPF0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPF1(0),
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.ngpio = EXYNOS4_GPIO_F1_NR,
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.label = "GPF1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPF2(0),
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.ngpio = EXYNOS4_GPIO_F2_NR,
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.label = "GPF2",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPF3(0),
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.ngpio = EXYNOS4_GPIO_F3_NR,
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.label = "GPF3",
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},
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},
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};
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static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
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{
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.chip = {
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.base = EXYNOS4_GPJ0(0),
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.ngpio = EXYNOS4_GPIO_J0_NR,
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.label = "GPJ0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPJ1(0),
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.ngpio = EXYNOS4_GPIO_J1_NR,
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.label = "GPJ1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPK0(0),
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.ngpio = EXYNOS4_GPIO_K0_NR,
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.label = "GPK0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPK1(0),
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.ngpio = EXYNOS4_GPIO_K1_NR,
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.label = "GPK1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPK2(0),
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.ngpio = EXYNOS4_GPIO_K2_NR,
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.label = "GPK2",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPK3(0),
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.ngpio = EXYNOS4_GPIO_K3_NR,
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.label = "GPK3",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPL0(0),
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.ngpio = EXYNOS4_GPIO_L0_NR,
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.label = "GPL0",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPL1(0),
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.ngpio = EXYNOS4_GPIO_L1_NR,
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.label = "GPL1",
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},
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}, {
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.chip = {
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.base = EXYNOS4_GPL2(0),
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.ngpio = EXYNOS4_GPIO_L2_NR,
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.label = "GPL2",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = EXYNOS4_GPY0(0),
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.ngpio = EXYNOS4_GPIO_Y0_NR,
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.label = "GPY0",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = EXYNOS4_GPY1(0),
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.ngpio = EXYNOS4_GPIO_Y1_NR,
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.label = "GPY1",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = EXYNOS4_GPY2(0),
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.ngpio = EXYNOS4_GPIO_Y2_NR,
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.label = "GPY2",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = EXYNOS4_GPY3(0),
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.ngpio = EXYNOS4_GPIO_Y3_NR,
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.label = "GPY3",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = EXYNOS4_GPY4(0),
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.ngpio = EXYNOS4_GPIO_Y4_NR,
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.label = "GPY4",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = EXYNOS4_GPY5(0),
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.ngpio = EXYNOS4_GPIO_Y5_NR,
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.label = "GPY5",
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},
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}, {
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.config = &gpio_cfg_noint,
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.chip = {
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.base = EXYNOS4_GPY6(0),
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.ngpio = EXYNOS4_GPIO_Y6_NR,
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.label = "GPY6",
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},
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}, {
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.base = (S5P_VA_GPIO2 + 0xC00),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(0),
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.chip = {
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.base = EXYNOS4_GPX0(0),
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.ngpio = EXYNOS4_GPIO_X0_NR,
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.label = "GPX0",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO2 + 0xC20),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(8),
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.chip = {
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.base = EXYNOS4_GPX1(0),
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.ngpio = EXYNOS4_GPIO_X1_NR,
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.label = "GPX1",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO2 + 0xC40),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(16),
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.chip = {
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.base = EXYNOS4_GPX2(0),
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.ngpio = EXYNOS4_GPIO_X2_NR,
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.label = "GPX2",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO2 + 0xC60),
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.config = &gpio_cfg_noint,
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.irq_base = IRQ_EINT(24),
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.chip = {
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.base = EXYNOS4_GPX3(0),
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.ngpio = EXYNOS4_GPIO_X3_NR,
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.label = "GPX3",
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.to_irq = samsung_gpiolib_to_irq,
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},
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},
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};
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static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
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{
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.chip = {
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.base = EXYNOS4_GPZ(0),
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.ngpio = EXYNOS4_GPIO_Z_NR,
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.label = "GPZ",
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},
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},
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};
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static __init int exynos4_gpiolib_init(void)
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{
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struct s3c_gpio_chip *chip;
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int i;
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int group = 0;
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int nr_chips;
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/* GPIO part 1 */
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chip = exynos4_gpio_part1_4bit;
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nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
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for (i = 0; i < nr_chips; i++, chip++) {
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if (chip->config == NULL) {
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chip->config = &gpio_cfg;
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/* Assign the GPIO interrupt group */
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chip->group = group++;
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}
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if (chip->base == NULL)
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chip->base = S5P_VA_GPIO1 + (i) * 0x20;
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}
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samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
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/* GPIO part 2 */
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chip = exynos4_gpio_part2_4bit;
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nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
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for (i = 0; i < nr_chips; i++, chip++) {
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if (chip->config == NULL) {
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chip->config = &gpio_cfg;
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/* Assign the GPIO interrupt group */
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chip->group = group++;
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}
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if (chip->base == NULL)
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chip->base = S5P_VA_GPIO2 + (i) * 0x20;
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}
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samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
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/* GPIO part 3 */
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chip = exynos4_gpio_part3_4bit;
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nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
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for (i = 0; i < nr_chips; i++, chip++) {
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if (chip->config == NULL) {
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chip->config = &gpio_cfg;
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/* Assign the GPIO interrupt group */
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chip->group = group++;
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}
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if (chip->base == NULL)
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chip->base = S5P_VA_GPIO3 + (i) * 0x20;
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}
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samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
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s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
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s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
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return 0;
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}
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core_initcall(exynos4_gpiolib_init);
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