mirror of
https://github.com/edk2-porting/linux-next.git
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288 lines
8.0 KiB
C
288 lines
8.0 KiB
C
/*
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* Copyright (C) 2004 IBM
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*
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* Implements the generic device dma API for powerpc.
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* the pci and vio busses
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*/
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#ifndef _ASM_DMA_MAPPING_H
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#define _ASM_DMA_MAPPING_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/cache.h>
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/* need struct page definitions */
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#include <linux/mm.h>
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#include <asm/scatterlist.h>
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#include <asm/io.h>
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#include <asm/bug.h>
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#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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#ifdef CONFIG_NOT_COHERENT_CACHE
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/*
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* DMA-consistent mapping functions for PowerPCs that don't support
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* cache snooping. These allocate/free a region of uncached mapped
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* memory space for use with DMA devices. Alternatively, you could
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* allocate the space "normally" and use the cache management functions
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* to ensure it is consistent.
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*/
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extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
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extern void __dma_free_coherent(size_t size, void *vaddr);
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extern void __dma_sync(void *vaddr, size_t size, int direction);
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extern void __dma_sync_page(struct page *page, unsigned long offset,
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size_t size, int direction);
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#else /* ! CONFIG_NOT_COHERENT_CACHE */
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/*
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* Cache coherent cores.
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*/
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#define __dma_alloc_coherent(gfp, size, handle) NULL
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#define __dma_free_coherent(size, addr) do { } while (0)
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#define __dma_sync(addr, size, rw) do { } while (0)
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#define __dma_sync_page(pg, off, sz, rw) do { } while (0)
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#endif /* ! CONFIG_NOT_COHERENT_CACHE */
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#ifdef CONFIG_PPC64
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extern int dma_supported(struct device *dev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 dma_mask);
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extern void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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extern void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_handle);
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extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
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size_t size, enum dma_data_direction direction);
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extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction);
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extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction);
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extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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size_t size, enum dma_data_direction direction);
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extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction direction);
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extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
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int nhwentries, enum dma_data_direction direction);
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#else /* CONFIG_PPC64 */
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#define dma_supported(dev, mask) (1)
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static inline int dma_set_mask(struct device *dev, u64 dma_mask)
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{
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if (!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = dma_mask;
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return 0;
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}
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static inline void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t * dma_handle,
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gfp_t gfp)
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{
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#ifdef CONFIG_NOT_COHERENT_CACHE
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return __dma_alloc_coherent(size, dma_handle, gfp);
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#else
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void *ret;
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/* ignore region specifiers */
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gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
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if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
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gfp |= GFP_DMA;
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ret = (void *)__get_free_pages(gfp, get_order(size));
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if (ret != NULL) {
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memset(ret, 0, size);
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*dma_handle = virt_to_bus(ret);
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}
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return ret;
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#endif
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}
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static inline void
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dma_free_coherent(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle)
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{
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#ifdef CONFIG_NOT_COHERENT_CACHE
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__dma_free_coherent(size, vaddr);
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#else
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free_pages((unsigned long)vaddr, get_order(size));
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#endif
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}
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static inline dma_addr_t
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dma_map_single(struct device *dev, void *ptr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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__dma_sync(ptr, size, direction);
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return virt_to_bus(ptr);
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}
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/* We do nothing. */
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#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
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static inline dma_addr_t
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dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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__dma_sync_page(page, offset, size, direction);
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return page_to_bus(page) + offset;
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}
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/* We do nothing. */
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#define dma_unmap_page(dev, handle, size, dir) do { } while (0)
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static inline int
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dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction direction)
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{
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int i;
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BUG_ON(direction == DMA_NONE);
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for (i = 0; i < nents; i++, sg++) {
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BUG_ON(!sg->page);
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__dma_sync_page(sg->page, sg->offset, sg->length, direction);
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sg->dma_address = page_to_bus(sg->page) + sg->offset;
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}
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return nents;
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}
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/* We don't do anything here. */
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#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
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#endif /* CONFIG_PPC64 */
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static inline void dma_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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__dma_sync(bus_to_virt(dma_handle), size, direction);
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}
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static inline void dma_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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__dma_sync(bus_to_virt(dma_handle), size, direction);
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}
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static inline void dma_sync_sg_for_cpu(struct device *dev,
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struct scatterlist *sg, int nents,
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enum dma_data_direction direction)
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{
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int i;
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BUG_ON(direction == DMA_NONE);
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for (i = 0; i < nents; i++, sg++)
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__dma_sync_page(sg->page, sg->offset, sg->length, direction);
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}
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static inline void dma_sync_sg_for_device(struct device *dev,
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struct scatterlist *sg, int nents,
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enum dma_data_direction direction)
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{
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int i;
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BUG_ON(direction == DMA_NONE);
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for (i = 0; i < nents; i++, sg++)
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__dma_sync_page(sg->page, sg->offset, sg->length, direction);
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}
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static inline int dma_mapping_error(dma_addr_t dma_addr)
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{
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#ifdef CONFIG_PPC64
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return (dma_addr == DMA_ERROR_CODE);
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#else
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return 0;
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#endif
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#ifdef CONFIG_NOT_COHERENT_CACHE
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#define dma_is_consistent(d) (0)
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#else
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#define dma_is_consistent(d) (1)
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#endif
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static inline int dma_get_cache_alignment(void)
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{
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#ifdef CONFIG_PPC64
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/* no easy way to get cache size on all processors, so return
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* the maximum possible, to be safe */
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return (1 << INTERNODE_CACHE_SHIFT);
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#else
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/*
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* Each processor family will define its own L1_CACHE_SHIFT,
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* L1_CACHE_BYTES wraps to this, so this is always safe.
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*/
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return L1_CACHE_BYTES;
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#endif
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}
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static inline void dma_sync_single_range_for_cpu(struct device *dev,
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dma_addr_t dma_handle, unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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/* just sync everything for now */
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dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
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}
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static inline void dma_sync_single_range_for_device(struct device *dev,
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dma_addr_t dma_handle, unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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/* just sync everything for now */
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dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
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}
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static inline void dma_cache_sync(void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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__dma_sync(vaddr, size, (int)direction);
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}
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/*
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* DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
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*/
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struct dma_mapping_ops {
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void * (*alloc_coherent)(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag);
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void (*free_coherent)(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle);
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dma_addr_t (*map_single)(struct device *dev, void *ptr,
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size_t size, enum dma_data_direction direction);
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void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction);
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int (*map_sg)(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction);
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void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction);
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int (*dma_supported)(struct device *dev, u64 mask);
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int (*dac_dma_supported)(struct device *dev, u64 mask);
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};
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#endif /* __KERNEL__ */
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#endif /* _ASM_DMA_MAPPING_H */
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