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5d942ce63c
The snd_hdac_chip_readl return can never be less than zeros, so no point in checking for the return value This fixes following static checker warnings in snd_hdac_ext_bus_parse_capabilities sound/hda/ext/hdac_ext_controller.c:47 snd_hdac_ext_bus_parse_capabilities() warn: unsigned 'offset' is never less than zero. sound/hda/ext/hdac_ext_controller.c:54 snd_hdac_ext_bus_parse_capabilities() warn: unsigned 'cur_cap' is never less than zero. Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
283 lines
7.3 KiB
C
283 lines
7.3 KiB
C
/*
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* hdac-ext-controller.c - HD-audio extended controller functions.
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*
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* Copyright (C) 2014-2015 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <sound/hda_register.h>
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#include <sound/hdaudio_ext.h>
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/*
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* maximum HDAC capablities we should parse to avoid endless looping:
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* currently we have 4 extended caps, so this is future proof for now.
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* extend when this limit is seen meeting in real HW
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*/
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#define HDAC_MAX_CAPS 10
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/**
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* snd_hdac_ext_bus_parse_capabilities - parse capablity structure
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* @ebus: the pointer to extended bus object
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*
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* Returns 0 if successful, or a negative error code.
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*/
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int snd_hdac_ext_bus_parse_capabilities(struct hdac_ext_bus *ebus)
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{
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unsigned int cur_cap;
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unsigned int offset;
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struct hdac_bus *bus = &ebus->bus;
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unsigned int counter = 0;
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offset = snd_hdac_chip_readl(bus, LLCH);
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/* Lets walk the linked capabilities list */
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do {
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cur_cap = _snd_hdac_chip_read(l, bus, offset);
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dev_dbg(bus->dev, "Capability version: 0x%x\n",
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((cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF));
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dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
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(cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
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switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
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case AZX_ML_CAP_ID:
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dev_dbg(bus->dev, "Found ML capability\n");
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ebus->mlcap = bus->remap_addr + offset;
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break;
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case AZX_GTS_CAP_ID:
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dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
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ebus->gtscap = bus->remap_addr + offset;
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break;
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case AZX_PP_CAP_ID:
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/* PP capability found, the Audio DSP is present */
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dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
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ebus->ppcap = bus->remap_addr + offset;
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break;
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case AZX_SPB_CAP_ID:
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/* SPIB capability found, handler function */
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dev_dbg(bus->dev, "Found SPB capability\n");
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ebus->spbcap = bus->remap_addr + offset;
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break;
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default:
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dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
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break;
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}
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counter++;
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if (counter > HDAC_MAX_CAPS) {
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dev_err(bus->dev, "We exceeded HDAC Ext capablities!!!\n");
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break;
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}
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/* read the offset of next capabiity */
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offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
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} while (offset);
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return 0;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_parse_capabilities);
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/*
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* processing pipe helpers - these helpers are useful for dealing with HDA
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* new capability of processing pipelines
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*/
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/**
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* snd_hdac_ext_bus_ppcap_enable - enable/disable processing pipe capability
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* @ebus: HD-audio extended core bus
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* @enable: flag to turn on/off the capability
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*/
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void snd_hdac_ext_bus_ppcap_enable(struct hdac_ext_bus *ebus, bool enable)
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{
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struct hdac_bus *bus = &ebus->bus;
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if (!ebus->ppcap) {
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dev_err(bus->dev, "Address of PP capability is NULL");
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return;
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}
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if (enable)
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snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, 0, AZX_PPCTL_GPROCEN);
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else
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snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, AZX_PPCTL_GPROCEN, 0);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_ppcap_enable);
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/**
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* snd_hdac_ext_bus_ppcap_int_enable - ppcap interrupt enable/disable
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* @ebus: HD-audio extended core bus
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* @enable: flag to enable/disable interrupt
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*/
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void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_ext_bus *ebus, bool enable)
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{
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struct hdac_bus *bus = &ebus->bus;
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if (!ebus->ppcap) {
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dev_err(bus->dev, "Address of PP capability is NULL\n");
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return;
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}
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if (enable)
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snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, 0, AZX_PPCTL_PIE);
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else
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snd_hdac_updatel(ebus->ppcap, AZX_REG_PP_PPCTL, AZX_PPCTL_PIE, 0);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_ppcap_int_enable);
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/*
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* Multilink helpers - these helpers are useful for dealing with HDA
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* new multilink capability
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*/
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/**
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* snd_hdac_ext_bus_get_ml_capabilities - get multilink capability
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* @ebus: HD-audio extended core bus
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*
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* This will parse all links and read the mlink capabilities and add them
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* in hlink_list of extended hdac bus
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* Note: this will be freed on bus exit by driver
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*/
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int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_ext_bus *ebus)
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{
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int idx;
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u32 link_count;
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struct hdac_ext_link *hlink;
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struct hdac_bus *bus = &ebus->bus;
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link_count = readl(ebus->mlcap + AZX_REG_ML_MLCD) + 1;
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dev_dbg(bus->dev, "In %s Link count: %d\n", __func__, link_count);
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for (idx = 0; idx < link_count; idx++) {
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hlink = kzalloc(sizeof(*hlink), GFP_KERNEL);
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if (!hlink)
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return -ENOMEM;
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hlink->index = idx;
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hlink->bus = bus;
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hlink->ml_addr = ebus->mlcap + AZX_ML_BASE +
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(AZX_ML_INTERVAL * idx);
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hlink->lcaps = snd_hdac_chip_readl(bus, ML_LCAP);
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hlink->lsdiid = snd_hdac_chip_readw(bus, ML_LSDIID);
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list_add_tail(&hlink->list, &ebus->hlink_list);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_get_ml_capabilities);
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/**
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* snd_hdac_link_free_all- free hdac extended link objects
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*
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* @ebus: HD-audio ext core bus
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*/
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void snd_hdac_link_free_all(struct hdac_ext_bus *ebus)
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{
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struct hdac_ext_link *l;
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while (!list_empty(&ebus->hlink_list)) {
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l = list_first_entry(&ebus->hlink_list, struct hdac_ext_link, list);
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list_del(&l->list);
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kfree(l);
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}
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}
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EXPORT_SYMBOL_GPL(snd_hdac_link_free_all);
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/**
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* snd_hdac_ext_bus_get_link_index - get link based on codec name
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* @ebus: HD-audio extended core bus
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* @codec_name: codec name
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*/
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struct hdac_ext_link *snd_hdac_ext_bus_get_link(struct hdac_ext_bus *ebus,
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const char *codec_name)
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{
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int i;
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struct hdac_ext_link *hlink = NULL;
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int bus_idx, addr;
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if (sscanf(codec_name, "ehdaudio%dD%d", &bus_idx, &addr) != 2)
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return NULL;
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if (ebus->idx != bus_idx)
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return NULL;
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list_for_each_entry(hlink, &ebus->hlink_list, list) {
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for (i = 0; i < HDA_MAX_CODECS; i++) {
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if (hlink->lsdiid & (0x1 << addr))
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return hlink;
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}
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}
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return NULL;
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_get_link);
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static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
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{
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int timeout;
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u32 val;
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int mask = (1 << AZX_MLCTL_CPA);
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udelay(3);
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timeout = 50;
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do {
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val = snd_hdac_chip_readl(link->bus, ML_LCTL);
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if (enable) {
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if (((val & mask) >> AZX_MLCTL_CPA))
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return 0;
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} else {
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if (!((val & mask) >> AZX_MLCTL_CPA))
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return 0;
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}
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udelay(3);
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} while (--timeout);
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return -EIO;
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}
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/**
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* snd_hdac_ext_bus_link_power_up -power up hda link
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* @link: HD-audio extended link
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*/
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int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *link)
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{
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snd_hdac_chip_updatel(link->bus, ML_LCTL, 0, AZX_MLCTL_SPA);
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return check_hdac_link_power_active(link, true);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up);
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/**
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* snd_hdac_ext_bus_link_power_down -power down hda link
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* @link: HD-audio extended link
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*/
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int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link)
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{
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snd_hdac_chip_updatel(link->bus, ML_LCTL, AZX_MLCTL_SPA, 0);
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return check_hdac_link_power_active(link, false);
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}
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EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_down);
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