mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-26 22:24:09 +08:00
30e748a507
This matters to any sort of device that is wired to one of the CPU interrupt pins on an SMP system. Typically the scenario is most easily triggered with the count/compare timer interrupt where the same interrupt number and thus irq_desc is used on each processor. CPU A CPU B do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) set IRQ_INPROGRESS spin_unlock(desc_lock) do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) IRQ_INPROGRESS set => bail out spin_lock(desc_lock) clear IRQ_INPROGRESS spin_unlock(desc_lock) In case of the cp0 compare interrupt this means the interrupt will be acked and not handled or re-armed on CPU b, so there won't be any timer interrupt until the count register wraps around. With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just working right on VSMP because the count registers are synchronized on bootup so it takes something that disables interrupts for a long time on one processor to trigger this one. For scenarios where an interrupt is multicasted or broadcasted over several CPUs the existing code was safe and the fix will break it. There is no way to know in the interrupt controller code because it is abstracted from the platform code. I think we do not have such a setup currently, so this should be ok. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/*
|
|
* Copyright 2001 MontaVista Software Inc.
|
|
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
|
|
*
|
|
* Copyright (C) 2001 Ralf Baechle
|
|
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
|
|
* Author: Maciej W. Rozycki <macro@mips.com>
|
|
*
|
|
* This file define the irq handler for MIPS CPU interrupts.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/*
|
|
* Almost all MIPS CPUs define 8 interrupt sources. They are typically
|
|
* level triggered (i.e., cannot be cleared from CPU; must be cleared from
|
|
* device). The first two are software interrupts which we don't really
|
|
* use or support. The last one is usually the CPU timer interrupt if
|
|
* counter register is present or, for CPUs with an external FPU, by
|
|
* convention it's the FPU exception interrupt.
|
|
*
|
|
* Don't even think about using this on SMP. You have been warned.
|
|
*
|
|
* This file exports one global function:
|
|
* void mips_cpu_irq_init(void);
|
|
*/
|
|
#include <linux/init.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/kernel.h>
|
|
|
|
#include <asm/irq_cpu.h>
|
|
#include <asm/mipsregs.h>
|
|
#include <asm/mipsmtregs.h>
|
|
#include <asm/system.h>
|
|
|
|
static inline void unmask_mips_irq(unsigned int irq)
|
|
{
|
|
set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
|
|
irq_enable_hazard();
|
|
}
|
|
|
|
static inline void mask_mips_irq(unsigned int irq)
|
|
{
|
|
clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
|
|
irq_disable_hazard();
|
|
}
|
|
|
|
static struct irq_chip mips_cpu_irq_controller = {
|
|
.name = "MIPS",
|
|
.ack = mask_mips_irq,
|
|
.mask = mask_mips_irq,
|
|
.mask_ack = mask_mips_irq,
|
|
.unmask = unmask_mips_irq,
|
|
.eoi = unmask_mips_irq,
|
|
};
|
|
|
|
/*
|
|
* Basically the same as above but taking care of all the MT stuff
|
|
*/
|
|
|
|
#define unmask_mips_mt_irq unmask_mips_irq
|
|
#define mask_mips_mt_irq mask_mips_irq
|
|
|
|
static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
|
|
{
|
|
unsigned int vpflags = dvpe();
|
|
|
|
clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
|
|
evpe(vpflags);
|
|
unmask_mips_mt_irq(irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* While we ack the interrupt interrupts are disabled and thus we don't need
|
|
* to deal with concurrency issues. Same for mips_cpu_irq_end.
|
|
*/
|
|
static void mips_mt_cpu_irq_ack(unsigned int irq)
|
|
{
|
|
unsigned int vpflags = dvpe();
|
|
clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
|
|
evpe(vpflags);
|
|
mask_mips_mt_irq(irq);
|
|
}
|
|
|
|
static struct irq_chip mips_mt_cpu_irq_controller = {
|
|
.name = "MIPS",
|
|
.startup = mips_mt_cpu_irq_startup,
|
|
.ack = mips_mt_cpu_irq_ack,
|
|
.mask = mask_mips_mt_irq,
|
|
.mask_ack = mips_mt_cpu_irq_ack,
|
|
.unmask = unmask_mips_mt_irq,
|
|
.eoi = unmask_mips_mt_irq,
|
|
};
|
|
|
|
void __init mips_cpu_irq_init(void)
|
|
{
|
|
int irq_base = MIPS_CPU_IRQ_BASE;
|
|
int i;
|
|
|
|
/* Mask interrupts. */
|
|
clear_c0_status(ST0_IM);
|
|
clear_c0_cause(CAUSEF_IP);
|
|
|
|
/*
|
|
* Only MT is using the software interrupts currently, so we just
|
|
* leave them uninitialized for other processors.
|
|
*/
|
|
if (cpu_has_mipsmt)
|
|
for (i = irq_base; i < irq_base + 2; i++)
|
|
set_irq_chip(i, &mips_mt_cpu_irq_controller);
|
|
|
|
for (i = irq_base + 2; i < irq_base + 8; i++)
|
|
set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
|
|
handle_percpu_irq);
|
|
}
|