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f72ed4beb1
The field will be removed from the sh-sci driver. Don't set it and let the driver handle baud rate calculation internally. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
233 lines
7.4 KiB
C
233 lines
7.4 KiB
C
/*
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* r8a7791 processor support
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a7791.h>
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#include <mach/rcar-gen2.h>
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#include <asm/mach/arch.h>
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static const struct resource pfc_resources[] __initconst = {
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DEFINE_RES_MEM(0xe6060000, 0x250),
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};
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#define r8a7791_register_pfc() \
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platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
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ARRAY_SIZE(pfc_resources))
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#define R8A7791_GPIO(idx, base, nr) \
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static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
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DEFINE_RES_MEM((base), 0x50), \
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DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
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}; \
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\
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static const struct gpio_rcar_config \
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r8a7791_gpio##idx##_platform_data __initconst = { \
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.gpio_base = 32 * (idx), \
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.irq_base = 0, \
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.number_of_pins = (nr), \
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.pctl_name = "pfc-r8a7791", \
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.has_both_edge_trigger = 1, \
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}; \
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R8A7791_GPIO(0, 0xe6050000, 32);
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R8A7791_GPIO(1, 0xe6051000, 32);
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R8A7791_GPIO(2, 0xe6052000, 32);
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R8A7791_GPIO(3, 0xe6053000, 32);
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R8A7791_GPIO(4, 0xe6054000, 32);
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R8A7791_GPIO(5, 0xe6055000, 32);
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R8A7791_GPIO(6, 0xe6055400, 32);
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R8A7791_GPIO(7, 0xe6055800, 26);
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#define r8a7791_register_gpio(idx) \
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platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
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r8a7791_gpio##idx##_resources, \
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ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
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&r8a7791_gpio##idx##_platform_data, \
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sizeof(r8a7791_gpio##idx##_platform_data))
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void __init r8a7791_pinmux_init(void)
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{
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r8a7791_register_pfc();
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r8a7791_register_gpio(0);
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r8a7791_register_gpio(1);
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r8a7791_register_gpio(2);
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r8a7791_register_gpio(3);
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r8a7791_register_gpio(4);
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r8a7791_register_gpio(5);
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r8a7791_register_gpio(6);
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r8a7791_register_gpio(7);
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}
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#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
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static struct plat_sci_port scif##index##_platform_data = { \
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.type = scif_type, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}; \
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\
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static struct resource scif##index##_resources[] = { \
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DEFINE_RES_MEM(baseaddr, 0x100), \
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DEFINE_RES_IRQ(irq), \
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}
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#define R8A7791_SCIF(index, baseaddr, irq) \
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__R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
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#define R8A7791_SCIFA(index, baseaddr, irq) \
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__R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
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#define R8A7791_SCIFB(index, baseaddr, irq) \
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__R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
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R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
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R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
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R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
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R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
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R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
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R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
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R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
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R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
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R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
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R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
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R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
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R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
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R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
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R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
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R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
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#define r8a7791_register_scif(index) \
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platform_device_register_resndata(&platform_bus, "sh-sci", index, \
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scif##index##_resources, \
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ARRAY_SIZE(scif##index##_resources), \
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&scif##index##_platform_data, \
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sizeof(scif##index##_platform_data))
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static const struct sh_timer_config cmt00_platform_data __initconst = {
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.name = "CMT00",
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.timer_bit = 0,
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.clockevent_rating = 80,
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};
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static const struct resource cmt00_resources[] __initconst = {
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DEFINE_RES_MEM(0xffca0510, 0x0c),
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DEFINE_RES_MEM(0xffca0500, 0x04),
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DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
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};
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#define r8a7791_register_cmt(idx) \
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platform_device_register_resndata(&platform_bus, "sh_cmt", \
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idx, cmt##idx##_resources, \
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ARRAY_SIZE(cmt##idx##_resources), \
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&cmt##idx##_platform_data, \
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sizeof(struct sh_timer_config))
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static struct renesas_irqc_config irqc0_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
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};
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static struct resource irqc0_resources[] = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
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DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
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DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
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DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
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DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
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DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
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};
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#define r8a7791_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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static const struct resource thermal_resources[] __initconst = {
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DEFINE_RES_MEM(0xe61f0000, 0x14),
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DEFINE_RES_MEM(0xe61f0100, 0x38),
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DEFINE_RES_IRQ(gic_spi(69)),
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};
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#define r8a7791_register_thermal() \
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platform_device_register_simple("rcar_thermal", -1, \
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thermal_resources, \
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ARRAY_SIZE(thermal_resources))
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void __init r8a7791_add_dt_devices(void)
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{
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r8a7791_register_scif(0);
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r8a7791_register_scif(1);
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r8a7791_register_scif(2);
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r8a7791_register_scif(3);
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r8a7791_register_scif(4);
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r8a7791_register_scif(5);
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r8a7791_register_scif(6);
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r8a7791_register_scif(7);
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r8a7791_register_scif(8);
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r8a7791_register_scif(9);
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r8a7791_register_scif(10);
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r8a7791_register_scif(11);
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r8a7791_register_scif(12);
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r8a7791_register_scif(13);
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r8a7791_register_scif(14);
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r8a7791_register_cmt(00);
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}
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void __init r8a7791_add_standard_devices(void)
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{
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r8a7791_add_dt_devices();
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r8a7791_register_irqc(0);
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r8a7791_register_thermal();
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}
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void __init r8a7791_init_early(void)
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{
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#ifndef CONFIG_ARM_ARCH_TIMER
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shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
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#endif
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}
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#ifdef CONFIG_USE_OF
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static const char *r8a7791_boards_compat_dt[] __initdata = {
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"renesas,r8a7791",
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NULL,
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};
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DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
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.smp = smp_ops(r8a7791_smp_ops),
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.init_early = r8a7791_init_early,
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.init_time = rcar_gen2_timer_init,
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.dt_compat = r8a7791_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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