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Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
204 lines
3.6 KiB
Plaintext
204 lines
3.6 KiB
Plaintext
* Samsung Exynos5420 Clock Controller
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The Exynos5420 clock controller generates and supplies clock to various
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controllers within the Exynos5420 SoC.
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Required Properties:
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- comptible: should be one of the following.
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- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume.
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[Core Clocks]
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Clock ID
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----------------------------
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fin_pll 1
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[Clock Gate for Special Clocks]
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Clock ID
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----------------------------
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sclk_uart0 128
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sclk_uart1 129
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sclk_uart2 130
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sclk_uart3 131
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sclk_mmc0 132
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sclk_mmc1 133
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sclk_mmc2 134
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sclk_spi0 135
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sclk_spi1 136
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sclk_spi2 137
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sclk_i2s1 138
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sclk_i2s2 139
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sclk_pcm1 140
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sclk_pcm2 141
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sclk_spdif 142
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sclk_hdmi 143
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sclk_pixel 144
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sclk_dp1 145
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sclk_mipi1 146
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sclk_fimd1 147
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sclk_maudio0 148
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sclk_maupcm0 149
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sclk_usbd300 150
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sclk_usbd301 151
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sclk_usbphy300 152
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sclk_usbphy301 153
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sclk_unipro 154
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sclk_pwm 155
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sclk_gscl_wa 156
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sclk_gscl_wb 157
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sclk_hdmiphy 158
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[Peripheral Clock Gates]
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Clock ID
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----------------------------
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aclk66_peric 256
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uart0 257
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uart1 258
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uart2 259
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uart3 260
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i2c0 261
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i2c1 262
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i2c2 263
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i2c3 264
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i2c4 265
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i2c5 266
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i2c6 267
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i2c7 268
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i2c_hdmi 269
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tsadc 270
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spi0 271
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spi1 272
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spi2 273
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keyif 274
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i2s1 275
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i2s2 276
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pcm1 277
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pcm2 278
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pwm 279
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spdif 280
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i2c8 281
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i2c9 282
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i2c10 283
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aclk66_psgen 300
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chipid 301
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sysreg 302
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tzpc0 303
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tzpc1 304
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tzpc2 305
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tzpc3 306
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tzpc4 307
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tzpc5 308
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tzpc6 309
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tzpc7 310
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tzpc8 311
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tzpc9 312
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hdmi_cec 313
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seckey 314
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mct 315
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wdt 316
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rtc 317
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tmu 318
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tmu_gpu 319
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pclk66_gpio 330
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aclk200_fsys2 350
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mmc0 351
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mmc1 352
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mmc2 353
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sromc 354
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ufs 355
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aclk200_fsys 360
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tsi 361
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pdma0 362
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pdma1 363
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rtic 364
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usbh20 365
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usbd300 366
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usbd301 377
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aclk400_mscl 380
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mscl0 381
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mscl1 382
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mscl2 383
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smmu_mscl0 384
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smmu_mscl1 385
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smmu_mscl2 386
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aclk333 400
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mfc 401
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smmu_mfcl 402
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smmu_mfcr 403
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aclk200_disp1 410
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dsim1 411
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dp1 412
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hdmi 413
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aclk300_disp1 420
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fimd1 421
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smmu_fimd1 422
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aclk166 430
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mixer 431
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aclk266 440
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rotator 441
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mdma1 442
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smmu_rotator 443
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smmu_mdma1 444
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aclk300_jpeg 450
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jpeg 451
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jpeg2 452
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smmu_jpeg 453
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aclk300_gscl 460
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smmu_gscl0 461
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smmu_gscl1 462
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gscl_wa 463
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gscl_wb 464
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gscl0 465
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gscl1 466
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clk_3aa 467
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aclk266_g2d 470
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sss 471
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slim_sss 472
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mdma0 473
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aclk333_g2d 480
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g2d 481
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aclk333_432_gscl 490
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smmu_3aa 491
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smmu_fimcl0 492
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smmu_fimcl1 493
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smmu_fimcl3 494
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fimc_lite3 495
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aclk_g3d 500
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g3d 501
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smmu_mixer 502
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Example 1: An example of a clock controller node is listed below.
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clock: clock-controller@0x10010000 {
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compatible = "samsung,exynos5420-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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Example 2: UART controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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serial@13820000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13820000 0x100>;
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interrupts = <0 54 0>;
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clocks = <&clock 259>, <&clock 130>;
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clock-names = "uart", "clk_uart_baud0";
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};
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