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21e4b0726d
This driver was entered into staging a few cycles ago because there was not time to integrate the Realtek version into the support routines in the kernel. Now that there is an effort to converg the code base from Linux and the Realtek repo, it is time to move this driver. In addition, all the updates included in the 06/28/2014 version of the Realtek drivers are included here. With this change, it will be necessary to delete the staging driver. That will be handled in a separate patch. As it impacts the staging tree, such a patch is sent to a different destination. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
95 lines
2.8 KiB
C
95 lines
2.8 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2009-2012 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __RTL8723E_PWRSEQCMD_H__
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#define __RTL8723E_PWRSEQCMD_H__
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#include "wifi.h"
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/*---------------------------------------------
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* 3 The value of cmd: 4 bits
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*---------------------------------------------
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*/
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#define PWR_CMD_READ 0x00
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#define PWR_CMD_WRITE 0x01
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#define PWR_CMD_POLLING 0x02
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#define PWR_CMD_DELAY 0x03
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#define PWR_CMD_END 0x04
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/* define the base address of each block */
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#define PWR_BASEADDR_MAC 0x00
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#define PWR_BASEADDR_USB 0x01
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#define PWR_BASEADDR_PCIE 0x02
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#define PWR_BASEADDR_SDIO 0x03
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#define PWR_INTF_SDIO_MSK BIT(0)
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#define PWR_INTF_USB_MSK BIT(1)
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#define PWR_INTF_PCI_MSK BIT(2)
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#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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#define PWR_FAB_TSMC_MSK BIT(0)
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#define PWR_FAB_UMC_MSK BIT(1)
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#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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#define PWR_CUT_TESTCHIP_MSK BIT(0)
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#define PWR_CUT_A_MSK BIT(1)
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#define PWR_CUT_B_MSK BIT(2)
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#define PWR_CUT_C_MSK BIT(3)
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#define PWR_CUT_D_MSK BIT(4)
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#define PWR_CUT_E_MSK BIT(5)
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#define PWR_CUT_F_MSK BIT(6)
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#define PWR_CUT_G_MSK BIT(7)
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#define PWR_CUT_ALL_MSK 0xFF
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enum pwrseq_delay_unit {
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PWRSEQ_DELAY_US,
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PWRSEQ_DELAY_MS,
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};
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struct wlan_pwr_cfg {
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u16 offset;
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u8 cut_msk;
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u8 fab_msk:4;
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u8 interface_msk:4;
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u8 base:4;
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u8 cmd:4;
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u8 msk;
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u8 value;
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};
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#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset)
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#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk)
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#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk)
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#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk)
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#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base)
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#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd)
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#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk)
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#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value)
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bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
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u8 fab_version, u8 interface_type,
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struct wlan_pwr_cfg pwrcfgcmd[]);
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#endif
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