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721154f972
Currently the clocksource and clockevent support for davinci platforms lives in mach-davinci. It hard-codes many things, uses global variables, implements functionalities unused by any platform and has code fragments scattered across many (often unrelated) files. Implement a new, modern and simplified timer driver and put it into drivers/clocksource. We still need to support legacy board files so export a config structure and a function that allows machine code to register the timer. The timer we're using is 64-bit but can be programmed in dual 32-bit mode (both chained and unchained). On all davinci SoCs except for da830 we're using both halves. Lower half for clockevents and upper half for clocksource. On da830 we're using the lower half for both with the help of a compare register. This patch contains the core code and support for clockevent. The clocksource code will be included in a subsequent patch. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* TI DaVinci clocksource driver
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*
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* Copyright (C) 2019 Texas Instruments
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* Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
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*/
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#ifndef __TIMER_DAVINCI_H__
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#define __TIMER_DAVINCI_H__
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#include <linux/clk.h>
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#include <linux/ioport.h>
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enum {
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DAVINCI_TIMER_CLOCKEVENT_IRQ,
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DAVINCI_TIMER_CLOCKSOURCE_IRQ,
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DAVINCI_TIMER_NUM_IRQS,
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};
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/**
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* struct davinci_timer_cfg - davinci clocksource driver configuration struct
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* @reg: register range resource
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* @irq: clockevent and clocksource interrupt resources
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* @cmp_off: if set - it specifies the compare register used for clockevent
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*
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* Note: if the compare register is specified, the driver will use the bottom
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* clock half for both clocksource and clockevent and the compare register
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* to generate event irqs. The user must supply the correct compare register
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* interrupt number.
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*
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* This is only used by da830 the DSP of which uses the top half. The timer
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* driver still configures the top half to run in free-run mode.
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*/
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struct davinci_timer_cfg {
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struct resource reg;
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struct resource irq[DAVINCI_TIMER_NUM_IRQS];
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unsigned int cmp_off;
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};
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int __init davinci_timer_register(struct clk *clk,
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const struct davinci_timer_cfg *data);
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#endif /* __TIMER_DAVINCI_H__ */
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