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445959821f
This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
218 lines
7.4 KiB
C
218 lines
7.4 KiB
C
/*
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* linux/include/asm-arm/arch-omap/io.h
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*
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* IO definitions for TI OMAP processors and boards
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*
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* Copied from linux/include/asm-arm/arch-sa1100/io.h
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* Copyright (C) 1997-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Modifications:
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* 06-12-1997 RMK Created.
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* 07-04-1999 RMK Major cleanup
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include <asm/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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/*
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* We don't actually have real ISA nor PCI buses, but there is so many
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* drivers out there that might just work if we fake them...
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*/
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#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
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#define __mem_pci(a) (a)
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/*
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* ----------------------------------------------------------------------------
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* I/O mapping
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* ----------------------------------------------------------------------------
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*/
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#define PCIO_BASE 0
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#if defined(CONFIG_ARCH_OMAP1)
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#define IO_PHYS 0xFFFB0000
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#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
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#define IO_SIZE 0x40000
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#define IO_VIRT (IO_PHYS - IO_OFFSET)
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#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
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#define io_p2v(pa) ((pa) - IO_OFFSET)
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#define io_v2p(va) ((va) + IO_OFFSET)
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#elif defined(CONFIG_ARCH_OMAP2)
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/* We map both L3 and L4 on OMAP2 */
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#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
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#define L3_24XX_VIRT 0xf8000000
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#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
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#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
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#define L4_24XX_VIRT 0xd8000000
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#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
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#ifdef CONFIG_ARCH_OMAP2430
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#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
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#define L4_WK_243X_VIRT 0xd9000000
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#define L4_WK_243X_SIZE SZ_1M
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#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
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#define OMAP243X_GPMC_VIRT 0xFE000000
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#define OMAP243X_GPMC_SIZE SZ_1M
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#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
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#define OMAP243X_SDRC_VIRT 0xFD000000
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#define OMAP243X_SDRC_SIZE SZ_1M
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#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
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#define OMAP243X_SMS_VIRT 0xFC000000
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#define OMAP243X_SMS_SIZE SZ_1M
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#endif
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#define IO_OFFSET 0x90000000
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#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
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#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
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#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
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/* DSP */
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#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
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#define DSP_MEM_24XX_VIRT 0xe0000000
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#define DSP_MEM_24XX_SIZE 0x28000
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#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
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#define DSP_IPI_24XX_VIRT 0xe1000000
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#define DSP_IPI_24XX_SIZE SZ_4K
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#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
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#define DSP_MMU_24XX_VIRT 0xe2000000
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#define DSP_MMU_24XX_SIZE SZ_4K
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#elif defined(CONFIG_ARCH_OMAP3)
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/* We map both L3 and L4 on OMAP3 */
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#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
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#define L3_34XX_VIRT 0xf8000000
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#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
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#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
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#define L4_34XX_VIRT 0xd8000000
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#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
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/*
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* Need to look at the Size 4M for L4.
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* VPOM3430 was not working for Int controller
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*/
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#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
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#define L4_WK_34XX_VIRT 0xd8300000
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#define L4_WK_34XX_SIZE SZ_1M
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#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
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#define L4_PER_34XX_VIRT 0xd9000000
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#define L4_PER_34XX_SIZE SZ_1M
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#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
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#define L4_EMU_34XX_VIRT 0xe4000000
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#define L4_EMU_34XX_SIZE SZ_64M
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#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
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#define OMAP34XX_GPMC_VIRT 0xFE000000
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#define OMAP34XX_GPMC_SIZE SZ_1M
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#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
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#define OMAP343X_SMS_VIRT 0xFC000000
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#define OMAP343X_SMS_SIZE SZ_1M
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#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
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#define OMAP343X_SDRC_VIRT 0xFD000000
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#define OMAP343X_SDRC_SIZE SZ_1M
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#define IO_OFFSET 0x90000000
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#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
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#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
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#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
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/* DSP */
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#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
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#define DSP_MEM_34XX_VIRT 0xe0000000
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#define DSP_MEM_34XX_SIZE 0x28000
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#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
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#define DSP_IPI_34XX_VIRT 0xe1000000
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#define DSP_IPI_34XX_SIZE SZ_4K
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#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
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#define DSP_MMU_34XX_VIRT 0xe2000000
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#define DSP_MMU_34XX_SIZE SZ_4K
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#endif
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#ifndef __ASSEMBLER__
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/*
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* Functions to access the OMAP IO region
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*
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* NOTE: - Use omap_read/write[bwl] for physical register addresses
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* - Use __raw_read/write[bwl]() for virtual register addresses
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* - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
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* - DO NOT use hardcoded virtual addresses to allow changing the
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* IO address space again if needed
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*/
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#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a))
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#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a))
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#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a))
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#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v))
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#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
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#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
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/* 16 bit uses LDRH/STRH, base +/- offset_8 */
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typedef struct { volatile u16 offset[256]; } __regbase16;
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#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
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->offset[((vaddr)&0xff)>>1]
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#define __REG16(paddr) __REGV16(io_p2v(paddr))
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/* 8/32 bit uses LDR/STR, base +/- offset_12 */
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typedef struct { volatile u8 offset[4096]; } __regbase8;
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#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \
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->offset[((vaddr)&4095)>>0]
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#define __REG8(paddr) __REGV8(io_p2v(paddr))
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typedef struct { volatile u32 offset[4096]; } __regbase32;
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#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
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->offset[((vaddr)&4095)>>2]
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#define __REG32(paddr) __REGV32(io_p2v(paddr))
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extern void omap1_map_common_io(void);
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extern void omap1_init_common_hw(void);
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extern void omap2_map_common_io(void);
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extern void omap2_init_common_hw(void);
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#else
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#define __REG8(paddr) io_p2v(paddr)
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#define __REG16(paddr) io_p2v(paddr)
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#define __REG32(paddr) io_p2v(paddr)
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#endif
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#endif
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