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c8a76cac19
The PRCM (Power/Reset/Clock Management) unit provides several clock devices: - AR100 clk: used to clock the Power Management co-processor - AHB0 clk: used to clock the AHB0 bus - APB0 clk and gates: used to clk peripherals connected to the APB0 bus Add support for these clks in a separate driver so that they can be probed as platform devices instead of registered during early init. This is needed to be able to probe PRCM MFD subdevices. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
100 lines
2.5 KiB
C
100 lines
2.5 KiB
C
/*
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* Copyright (C) 2014 Free Electrons
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*
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* License Terms: GNU General Public License v2
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* Allwinner A31 APB0 clock gates driver
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#define SUN6I_APB0_GATES_MAX_SIZE 32
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static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct clk_onecell_data *clk_data;
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const char *clk_parent;
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const char *clk_name;
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struct resource *r;
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void __iomem *reg;
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int gate_id;
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int ngates;
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int i;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(&pdev->dev, r);
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if (!reg)
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return PTR_ERR(reg);
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clk_parent = of_clk_get_parent_name(np, 0);
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if (!clk_parent)
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return -EINVAL;
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ngates = of_property_count_strings(np, "clock-output-names");
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if (ngates < 0)
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return ngates;
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if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE)
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return -EINVAL;
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clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->clks = devm_kzalloc(&pdev->dev,
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SUN6I_APB0_GATES_MAX_SIZE *
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sizeof(struct clk *),
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GFP_KERNEL);
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if (!clk_data->clks)
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return -ENOMEM;
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for (i = 0; i < ngates; i++) {
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of_property_read_string_index(np, "clock-output-names",
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i, &clk_name);
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gate_id = i;
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of_property_read_u32_index(np, "clock-indices", i, &gate_id);
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WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE);
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if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE)
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continue;
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clk_data->clks[gate_id] = clk_register_gate(&pdev->dev,
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clk_name,
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clk_parent, 0,
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reg, gate_id,
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0, NULL);
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WARN_ON(IS_ERR(clk_data->clks[gate_id]));
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}
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clk_data->clk_num = ngates;
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return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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}
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const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
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{ /* sentinel */ }
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};
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static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
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.driver = {
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.name = "sun6i-a31-apb0-gates-clk",
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.owner = THIS_MODULE,
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.of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
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},
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.probe = sun6i_a31_apb0_gates_clk_probe,
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};
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module_platform_driver(sun6i_a31_apb0_gates_clk_driver);
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MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
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MODULE_DESCRIPTION("Allwinner A31 APB0 gate clocks driver");
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MODULE_LICENSE("GPL v2");
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