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9945155143
This enables M64 window on P7IOC, which has been enabled on PHB3. Different from PHB3 where 16 M64 BARs are supported and each of them can be owned by one particular PE# exclusively or divided evenly to 256 segments, every P7IOC PHB has 16 M64 BARs and each of them are divided to 8 segments. So every P7IOC PHB supports 128 M64 segments in total. P7IOC has M64DT, which helps mapping one particular M64 segment# to arbitrary PE#. PHB3 doesn't have M64DT, indicating that one M64 segment can only be pinned to the fixed PE#. In order to unified M64 support M64 on P7IOC and PHB3, we just provide 128 M64 segments on every P7IOC PHB and each of them is pinned to the fixed PE# by bypassing the function of M64DT. In turn, we just need different phb->init_m64() for P7IOC and PHB3 and maps M64 segment in pnv_ioda_reserve_m64_pe() for P7IOC, most of the code are shared by them. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
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.. | ||
eeh-powernv.c | ||
idle.c | ||
Kconfig | ||
Makefile | ||
npu-dma.c | ||
opal-async.c | ||
opal-dump.c | ||
opal-elog.c | ||
opal-flash.c | ||
opal-hmi.c | ||
opal-irqchip.c | ||
opal-kmsg.c | ||
opal-lpc.c | ||
opal-memory-errors.c | ||
opal-msglog.c | ||
opal-nvram.c | ||
opal-power.c | ||
opal-prd.c | ||
opal-rtc.c | ||
opal-sensor.c | ||
opal-sysparam.c | ||
opal-tracepoints.c | ||
opal-wrappers.S | ||
opal-xscom.c | ||
opal.c | ||
pci-ioda.c | ||
pci.c | ||
pci.h | ||
powernv.h | ||
rng.c | ||
setup.c | ||
smp.c | ||
subcore-asm.S | ||
subcore.c | ||
subcore.h |