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4cdc2ec1da
To support HS200 and UHS-1, we need add a big hunk of code, as shown in the following patches. So a separate file for rockchip SOCs is suitable. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/of_address.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define RK3288_CLKGEN_DIV 2
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static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
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{
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*cmdr |= SDMMC_CMD_USE_HOLD_REG;
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}
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static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
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{
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host->bus_hz /= RK3288_CLKGEN_DIV;
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return 0;
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}
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static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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int ret;
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unsigned int cclkin;
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u32 bus_hz;
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/*
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* cclkin: source clock of mmc controller
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* bus_hz: card interface clock generated by CLKGEN
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* bus_hz = cclkin / RK3288_CLKGEN_DIV
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* ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
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*
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* Note: div can only be 0 or 1
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* if DDR50 8bit mode(only emmc work in 8bit mode),
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* div must be set 1
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*/
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if (ios->bus_width == MMC_BUS_WIDTH_8 &&
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ios->timing == MMC_TIMING_MMC_DDR52)
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cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
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else
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cclkin = ios->clock * RK3288_CLKGEN_DIV;
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ret = clk_set_rate(host->ciu_clk, cclkin);
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if (ret)
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dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
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bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
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if (bus_hz != host->bus_hz) {
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host->bus_hz = bus_hz;
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/* force dw_mci_setup_bus() */
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host->current_speed = 0;
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}
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}
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static const struct dw_mci_drv_data rk2928_drv_data = {
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.prepare_command = dw_mci_rockchip_prepare_command,
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};
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static const struct dw_mci_drv_data rk3288_drv_data = {
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.prepare_command = dw_mci_rockchip_prepare_command,
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.set_ios = dw_mci_rk3288_set_ios,
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.setup_clock = dw_mci_rk3288_setup_clock,
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};
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static const struct of_device_id dw_mci_rockchip_match[] = {
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{ .compatible = "rockchip,rk2928-dw-mshc",
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.data = &rk2928_drv_data },
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{ .compatible = "rockchip,rk3288-dw-mshc",
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.data = &rk3288_drv_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
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static int dw_mci_rockchip_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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if (!pdev->dev.of_node)
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return -ENODEV;
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match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
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drv_data = match->data;
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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#ifdef CONFIG_PM_SLEEP
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static int dw_mci_rockchip_suspend(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_suspend(host);
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}
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static int dw_mci_rockchip_resume(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_resume(host);
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}
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#endif /* CONFIG_PM_SLEEP */
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static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
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dw_mci_rockchip_suspend,
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dw_mci_rockchip_resume);
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static struct platform_driver dw_mci_rockchip_pltfm_driver = {
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.probe = dw_mci_rockchip_probe,
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.remove = __exit_p(dw_mci_pltfm_remove),
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.driver = {
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.name = "dwmmc_rockchip",
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.of_match_table = dw_mci_rockchip_match,
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.pm = &dw_mci_rockchip_pmops,
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},
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};
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module_platform_driver(dw_mci_rockchip_pltfm_driver);
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MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
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MODULE_ALIAS("platform:dwmmc-rockchip");
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MODULE_LICENSE("GPL v2");
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