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UltraSPARC has special sets of global registers which are switched to for certain trap types. There is one set for MMU related traps, one set of Interrupt Vector processing, and another set (called the Alternate globals) for all other trap types. For what seems like forever we've hard coded the values in some of these trap registers. Some examples include: 1) Interrupt Vector global %g6 holds current processors interrupt work struct where received interrupts are managed for IRQ handler dispatch. 2) MMU global %g7 holds the base of the page tables of the currently active address space. 3) Alternate global %g6 held the current_thread_info() value. Such hardcoding has resulted in some serious issues in many areas. There are some code sequences where having another register available would help clean up the implementation. Taking traps such as cross-calls from the OBP firmware requires some trick code sequences wherein we have to save away and restore all of the special sets of global registers when we enter/exit OBP. We were also using the IMMU TSB register on SMP to hold the per-cpu area base address, which doesn't work any longer now that we actually use the TSB facility of the cpu. The implementation is pretty straight forward. One tricky bit is getting the current processor ID as that is different on different cpu variants. We use a stub with a fancy calling convention which we patch at boot time. The calling convention is that the stub is branched to and the (PC - 4) to return to is in register %g1. The cpu number is left in %g6. This stub can be invoked by using the __GET_CPUID macro. We use an array of per-cpu trap state to store the current thread and physical address of the current address space's page tables. The TRAP_LOAD_THREAD_REG loads %g6 with the current thread from this table, it uses __GET_CPUID and also clobbers %g1. TRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load the current processor's IRQ software state into %g6. It also uses __GET_CPUID and clobbers %g1. Finally, TRAP_LOAD_PGD_PHYS loads the physical address base of the current address space's page tables into %g7, it clobbers %g1 and uses __GET_CPUID. Many refinements are possible, as well as some tuning, with this stuff in place. Signed-off-by: David S. Miller <davem@davemloft.net>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/* cpudata.h: Per-cpu parameters.
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*
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* Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
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*/
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#ifndef _SPARC64_CPUDATA_H
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#define _SPARC64_CPUDATA_H
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#ifndef __ASSEMBLY__
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#include <linux/percpu.h>
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#include <linux/threads.h>
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typedef struct {
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/* Dcache line 1 */
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unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
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unsigned int multiplier;
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unsigned int counter;
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unsigned int idle_volume;
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unsigned long clock_tick; /* %tick's per second */
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unsigned long udelay_val;
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/* Dcache line 2, rarely used */
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unsigned int dcache_size;
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unsigned int dcache_line_size;
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unsigned int icache_size;
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unsigned int icache_line_size;
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unsigned int ecache_size;
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unsigned int ecache_line_size;
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unsigned int __pad3;
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unsigned int __pad4;
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} cpuinfo_sparc;
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DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
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#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
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#define local_cpu_data() __get_cpu_var(__cpu_data)
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/* Trap handling code needs to get at a few critical values upon
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* trap entry and to process TSB misses. These cannot be in the
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* per_cpu() area as we really need to lock them into the TLB and
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* thus make them part of the main kernel image. As a result we
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* try to make this as small as possible.
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*
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* This is padded out and aligned to 64-bytes to avoid false sharing
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* on SMP.
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*/
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/* If you modify the size of this structure, please update
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* TRAP_BLOCK_SZ_SHIFT below.
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*/
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struct thread_info;
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struct trap_per_cpu {
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/* D-cache line 1 */
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struct thread_info *thread;
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unsigned long pgd_paddr;
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unsigned long __pad1[2];
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/* D-cache line 2 */
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unsigned long __pad2[4];
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} __attribute__((aligned(64)));
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extern struct trap_per_cpu trap_block[NR_CPUS];
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extern void init_cur_cpu_trap(void);
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extern void per_cpu_patch(void);
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#endif /* !(__ASSEMBLY__) */
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#define TRAP_PER_CPU_THREAD 0x00
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#define TRAP_PER_CPU_PGD_PADDR 0x08
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#define TRAP_BLOCK_SZ_SHIFT 6
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/* Clobbers %g1, loads %g6 with local processor's cpuid */
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#define __GET_CPUID \
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ba,pt %xcc, __get_cpu_id; \
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rd %pc, %g1;
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/* Clobbers %g1, current address space PGD phys address into %g7. */
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#define TRAP_LOAD_PGD_PHYS \
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__GET_CPUID \
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sllx %g6, TRAP_BLOCK_SZ_SHIFT, %g6; \
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sethi %hi(trap_block), %g7; \
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or %g7, %lo(trap_block), %g7; \
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add %g7, %g6, %g7; \
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ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7;
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/* Clobbers %g1, loads local processor's IRQ work area into %g6. */
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#define TRAP_LOAD_IRQ_WORK \
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__GET_CPUID \
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sethi %hi(__irq_work), %g1; \
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sllx %g6, 6, %g6; \
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or %g1, %lo(__irq_work), %g1; \
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add %g1, %g6, %g6;
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/* Clobbers %g1, loads %g6 with current thread info pointer. */
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#define TRAP_LOAD_THREAD_REG \
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__GET_CPUID \
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sllx %g6, TRAP_BLOCK_SZ_SHIFT, %g6; \
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sethi %hi(trap_block), %g1; \
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or %g1, %lo(trap_block), %g1; \
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ldx [%g1 + %g6], %g6;
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/* Given the current thread info pointer in %g6, load the per-cpu
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* area base of the current processor into %g5. REG1 and REG2 are
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* clobbered.
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*/
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#ifdef CONFIG_SMP
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#define LOAD_PER_CPU_BASE(REG1, REG2) \
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ldub [%g6 + TI_CPU], REG1; \
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sethi %hi(__per_cpu_shift), %g5; \
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sethi %hi(__per_cpu_base), REG2; \
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ldx [%g5 + %lo(__per_cpu_shift)], %g5; \
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ldx [REG2 + %lo(__per_cpu_base)], REG2; \
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sllx REG1, %g5, %g5; \
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add %g5, REG2, %g5;
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#else
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#define LOAD_PER_CPU_BASE(REG1, REG2)
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#endif
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#endif /* _SPARC64_CPUDATA_H */
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