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c04c77540a
The v7_invalidate_l1 was used for the L1 cache that come out from reset in a undefined state. This is no need for Cortex-A15. We do it for A9 only. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
13 lines
281 B
ArmAsm
13 lines
281 B
ArmAsm
#include <linux/linkage.h>
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#include <linux/init.h>
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#include "sleep.h"
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.section ".text.head", "ax"
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ENTRY(tegra_secondary_startup)
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check_cpu_part_num 0xc09, r8, r9
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bleq v7_invalidate_l1
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b secondary_startup
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ENDPROC(tegra_secondary_startup)
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