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https://github.com/edk2-porting/linux-next.git
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3fde0e16d0
This patch adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Tejas Patel <tejasp@xilinx.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Acked-by: Olof Johansson <olof@lixom.net> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Xilinx Zynq MPSoC Firmware layer
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*
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* Copyright (C) 2014-2018 Xilinx
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Davorin Mista <davorin.mista@aggios.com>
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* Jolly Shah <jollys@xilinx.com>
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* Rajan Vaja <rajanv@xilinx.com>
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*/
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#ifndef __FIRMWARE_ZYNQMP_H__
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#define __FIRMWARE_ZYNQMP_H__
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#define ZYNQMP_PM_VERSION_MAJOR 1
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#define ZYNQMP_PM_VERSION_MINOR 0
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#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
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ZYNQMP_PM_VERSION_MINOR)
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#define ZYNQMP_TZ_VERSION_MAJOR 1
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#define ZYNQMP_TZ_VERSION_MINOR 0
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#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
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ZYNQMP_TZ_VERSION_MINOR)
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/* SMC SIP service Call Function Identifier Prefix */
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#define PM_SIP_SVC 0xC2000000
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#define PM_GET_TRUSTZONE_VERSION 0xa03
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/* Number of 32bits values in payload */
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#define PAYLOAD_ARG_CNT 4U
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enum pm_api_id {
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PM_GET_API_VERSION = 1,
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PM_IOCTL = 34,
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PM_QUERY_DATA,
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PM_CLOCK_ENABLE,
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PM_CLOCK_DISABLE,
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PM_CLOCK_GETSTATE,
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PM_CLOCK_SETDIVIDER,
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PM_CLOCK_GETDIVIDER,
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PM_CLOCK_SETRATE,
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PM_CLOCK_GETRATE,
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PM_CLOCK_SETPARENT,
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PM_CLOCK_GETPARENT,
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};
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/* PMU-FW return status codes */
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enum pm_ret_status {
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XST_PM_SUCCESS = 0,
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XST_PM_INTERNAL = 2000,
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XST_PM_CONFLICT,
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XST_PM_NO_ACCESS,
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XST_PM_INVALID_NODE,
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XST_PM_DOUBLE_REQ,
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XST_PM_ABORT_SUSPEND,
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};
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enum pm_ioctl_id {
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IOCTL_SET_PLL_FRAC_MODE = 8,
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IOCTL_GET_PLL_FRAC_MODE,
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IOCTL_SET_PLL_FRAC_DATA,
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IOCTL_GET_PLL_FRAC_DATA,
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};
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enum pm_query_id {
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PM_QID_INVALID,
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PM_QID_CLOCK_GET_NAME,
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PM_QID_CLOCK_GET_TOPOLOGY,
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PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
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PM_QID_CLOCK_GET_PARENTS,
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PM_QID_CLOCK_GET_ATTRIBUTES,
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PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
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};
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/**
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* struct zynqmp_pm_query_data - PM query data
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* @qid: query ID
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* @arg1: Argument 1 of query data
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* @arg2: Argument 2 of query data
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* @arg3: Argument 3 of query data
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*/
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struct zynqmp_pm_query_data {
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u32 qid;
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u32 arg1;
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u32 arg2;
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u32 arg3;
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};
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struct zynqmp_eemi_ops {
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int (*get_api_version)(u32 *version);
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int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
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int (*clock_enable)(u32 clock_id);
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int (*clock_disable)(u32 clock_id);
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int (*clock_getstate)(u32 clock_id, u32 *state);
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int (*clock_setdivider)(u32 clock_id, u32 divider);
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int (*clock_getdivider)(u32 clock_id, u32 *divider);
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int (*clock_setrate)(u32 clock_id, u64 rate);
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int (*clock_getrate)(u32 clock_id, u64 *rate);
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int (*clock_setparent)(u32 clock_id, u32 parent_id);
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int (*clock_getparent)(u32 clock_id, u32 *parent_id);
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int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
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};
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#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
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const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
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#else
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static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
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{
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return NULL;
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}
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#endif
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#endif /* __FIRMWARE_ZYNQMP_H__ */
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