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361c7ad607
As a consequence registers are now accessed with __raw_{read,write}[bl].
Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/*
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* include/asm-arm/arch-ns9xxx/clock.h
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*
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* Copyright (C) 2007 by Digi International Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H
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#include <asm/arch-ns9xxx/regs-sys.h>
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#define CRYSTAL 29491200 /* Hz */
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/* The HRM calls this value f_vco */
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static inline u32 ns9xxx_systemclock(void) __attribute__((const));
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static inline u32 ns9xxx_systemclock(void)
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{
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u32 pll = __raw_readl(SYS_PLL);
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/*
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* The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
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* time.c).
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*
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* The following values are given:
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* - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6}
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* - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2
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* - ND in {0 .. 31}
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* - FS in {0 .. 3}
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*
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* Assuming the worst, we consider:
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* - TIMERCLOCKSELECT == 64
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* - ND == 0
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* - FS == 3
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*
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* So HZ should be a divisor of:
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* (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT
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* == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64
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* == 2^8 * 3^2 * 5^2
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* == 57600
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*
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* Currently HZ is defined to be 100 for this platform.
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*
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* Fine.
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*/
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return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
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>> REGGETIM(pll, SYS_PLL, FS);
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}
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static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
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static inline u32 ns9xxx_cpuclock(void)
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{
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return ns9xxx_systemclock() / 2;
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}
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static inline u32 ns9xxx_ahbclock(void) __attribute__((const));
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static inline u32 ns9xxx_ahbclock(void)
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{
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return ns9xxx_systemclock() / 4;
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}
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static inline u32 ns9xxx_bbusclock(void) __attribute__((const));
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static inline u32 ns9xxx_bbusclock(void)
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{
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return ns9xxx_systemclock() / 8;
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}
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#endif /* ifndef __ASM_ARCH_CLOCK_H */
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