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f7018c2135
The drivers/video directory is a mess. It contains generic video related files, directories for backlight, console, linux logo, lots of fbdev device drivers, fbdev framework files. Make some order into the chaos by creating drivers/video/fbdev directory, and move all fbdev related files there. No functionality is changed, although I guess it is possible that some subtle Makefile build order related issue could be created by this patch. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Clark <robdclark@gmail.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
170 lines
3.9 KiB
C
170 lines
3.9 KiB
C
/*
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* linux/drivers/video/acornfb.h
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*
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* Copyright (C) 1998,1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Frame buffer code for Acorn platforms
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*/
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#if defined(HAS_VIDC20)
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#include <asm/hardware/iomd.h>
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#define VIDC_PALETTE_SIZE 256
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#define VIDC_NAME "VIDC20"
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#endif
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#define EXTEND8(x) ((x)|(x)<<8)
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#define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12)
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struct vidc20_palette {
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u_int red:8;
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u_int green:8;
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u_int blue:8;
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u_int ext:4;
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u_int unused:4;
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};
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struct vidc_palette {
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u_int red:4;
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u_int green:4;
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u_int blue:4;
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u_int trans:1;
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u_int sbz1:13;
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u_int reg:4;
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u_int sbz2:2;
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};
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union palette {
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struct vidc20_palette vidc20;
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struct vidc_palette vidc;
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u_int p;
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};
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struct acornfb_par {
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struct device *dev;
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unsigned long screen_end;
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unsigned int dram_size;
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unsigned int vram_half_sam;
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unsigned int palette_size;
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signed int montype;
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unsigned int using_vram : 1;
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unsigned int dpms : 1;
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union palette palette[VIDC_PALETTE_SIZE];
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u32 pseudo_palette[16];
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};
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struct vidc_timing {
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u_int h_cycle;
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u_int h_sync_width;
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u_int h_border_start;
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u_int h_display_start;
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u_int h_display_end;
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u_int h_border_end;
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u_int h_interlace;
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u_int v_cycle;
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u_int v_sync_width;
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u_int v_border_start;
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u_int v_display_start;
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u_int v_display_end;
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u_int v_border_end;
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u_int control;
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/* VIDC20 only */
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u_int pll_ctl;
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};
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struct modey_params {
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u_int y_res;
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u_int u_margin;
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u_int b_margin;
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u_int vsync_len;
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u_int vf;
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};
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struct modex_params {
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u_int x_res;
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u_int l_margin;
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u_int r_margin;
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u_int hsync_len;
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u_int clock;
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u_int hf;
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const struct modey_params *modey;
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};
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#ifdef HAS_VIDC20
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/*
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* VIDC20 registers
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*/
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#define VIDC20_CTRL 0xe0000000
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#define VIDC20_CTRL_PIX_VCLK (0 << 0)
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#define VIDC20_CTRL_PIX_HCLK (1 << 0)
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#define VIDC20_CTRL_PIX_RCLK (2 << 0)
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#define VIDC20_CTRL_PIX_CK (0 << 2)
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#define VIDC20_CTRL_PIX_CK2 (1 << 2)
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#define VIDC20_CTRL_PIX_CK3 (2 << 2)
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#define VIDC20_CTRL_PIX_CK4 (3 << 2)
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#define VIDC20_CTRL_PIX_CK5 (4 << 2)
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#define VIDC20_CTRL_PIX_CK6 (5 << 2)
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#define VIDC20_CTRL_PIX_CK7 (6 << 2)
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#define VIDC20_CTRL_PIX_CK8 (7 << 2)
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#define VIDC20_CTRL_1BPP (0 << 5)
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#define VIDC20_CTRL_2BPP (1 << 5)
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#define VIDC20_CTRL_4BPP (2 << 5)
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#define VIDC20_CTRL_8BPP (3 << 5)
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#define VIDC20_CTRL_16BPP (4 << 5)
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#define VIDC20_CTRL_32BPP (6 << 5)
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#define VIDC20_CTRL_FIFO_NS (0 << 8)
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#define VIDC20_CTRL_FIFO_4 (1 << 8)
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#define VIDC20_CTRL_FIFO_8 (2 << 8)
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#define VIDC20_CTRL_FIFO_12 (3 << 8)
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#define VIDC20_CTRL_FIFO_16 (4 << 8)
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#define VIDC20_CTRL_FIFO_20 (5 << 8)
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#define VIDC20_CTRL_FIFO_24 (6 << 8)
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#define VIDC20_CTRL_FIFO_28 (7 << 8)
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#define VIDC20_CTRL_INT (1 << 12)
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#define VIDC20_CTRL_DUP (1 << 13)
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#define VIDC20_CTRL_PDOWN (1 << 14)
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#define VIDC20_ECTL 0xc0000000
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#define VIDC20_ECTL_REG(x) ((x) & 0xf3)
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#define VIDC20_ECTL_ECK (1 << 2)
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#define VIDC20_ECTL_REDPED (1 << 8)
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#define VIDC20_ECTL_GREENPED (1 << 9)
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#define VIDC20_ECTL_BLUEPED (1 << 10)
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#define VIDC20_ECTL_DAC (1 << 12)
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#define VIDC20_ECTL_LCDGS (1 << 13)
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#define VIDC20_ECTL_HRM (1 << 14)
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#define VIDC20_ECTL_HS_MASK (3 << 16)
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#define VIDC20_ECTL_HS_HSYNC (0 << 16)
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#define VIDC20_ECTL_HS_NHSYNC (1 << 16)
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#define VIDC20_ECTL_HS_CSYNC (2 << 16)
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#define VIDC20_ECTL_HS_NCSYNC (3 << 16)
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#define VIDC20_ECTL_VS_MASK (3 << 18)
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#define VIDC20_ECTL_VS_VSYNC (0 << 18)
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#define VIDC20_ECTL_VS_NVSYNC (1 << 18)
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#define VIDC20_ECTL_VS_CSYNC (2 << 18)
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#define VIDC20_ECTL_VS_NCSYNC (3 << 18)
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#define VIDC20_DCTL 0xf0000000
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/* 0-9 = number of words in scanline */
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#define VIDC20_DCTL_SNA (1 << 12)
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#define VIDC20_DCTL_HDIS (1 << 13)
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#define VIDC20_DCTL_BUS_NS (0 << 16)
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#define VIDC20_DCTL_BUS_D31_0 (1 << 16)
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#define VIDC20_DCTL_BUS_D63_32 (2 << 16)
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#define VIDC20_DCTL_BUS_D63_0 (3 << 16)
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#define VIDC20_DCTL_VRAM_DIS (0 << 18)
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#define VIDC20_DCTL_VRAM_PXCLK (1 << 18)
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#define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18)
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#define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18)
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#endif
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