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0e0d499251
The corresponding hardware issues of CONFIG_ERRATA_SIFIVE_CIP_453 and CONFIG_ERRATA_SIFIVE_CIP_1200 only exist in the SiFive 64bit CPU cores. Therefore, these two errata are required only if CONFIG_64BIT=y Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Fixes:bff3ff5254("riscv: sifive: Apply errata "cip-1200" patch") Fixes:800149a77c("riscv: sifive: Apply errata "cip-453" patch") Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
45 lines
1.3 KiB
Plaintext
45 lines
1.3 KiB
Plaintext
menu "CPU errata selection"
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config RISCV_ERRATA_ALTERNATIVE
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bool "RISC-V alternative scheme"
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default y
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help
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This Kconfig allows the kernel to automatically patch the
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errata required by the execution platform at run time. The
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code patching is performed once in the boot stages. It means
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that the overhead from this mechanism is just taken once.
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config ERRATA_SIFIVE
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bool "SiFive errata"
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depends on RISCV_ERRATA_ALTERNATIVE
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help
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All SiFive errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all SiFive errata. Please say "Y"
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here if your platform uses SiFive CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_SIFIVE_CIP_453
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bool "Apply SiFive errata CIP-453"
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depends on ERRATA_SIFIVE && 64BIT
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default y
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help
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This will apply the SiFive CIP-453 errata to add sign extension
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to the $badaddr when exception type is instruction page fault
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and instruction access fault.
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If you don't know what to do here, say "Y".
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config ERRATA_SIFIVE_CIP_1200
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bool "Apply SiFive errata CIP-1200"
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depends on ERRATA_SIFIVE && 64BIT
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default y
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help
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This will apply the SiFive CIP-1200 errata to repalce all
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"sfence.vma addr" with "sfence.vma" to ensure that the addr
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has been flushed from TLB.
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If you don't know what to do here, say "Y".
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endmenu
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