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a36c61f902
We have flattened the BFA hierarchy and also reduced the number of source and header files we used to have earlier. Signed-off-by: Krishna Gudipati <kgudipat@brocade.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
237 lines
6.6 KiB
C
237 lines
6.6 KiB
C
/*
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* Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*
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* Linux driver for Brocade Fibre Channel Host Bus Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include "bfa_ioc.h"
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#include "bfi_cbreg.h"
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#include "bfa_defs.h"
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BFA_TRC_FILE(CNA, IOC_CB);
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/*
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* forward declarations
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*/
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static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
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static void bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc);
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static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
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struct bfa_ioc_hwif_s hwif_cb;
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/**
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* Called from bfa_ioc_attach() to map asic specific calls.
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*/
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void
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bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
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{
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hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
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hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
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hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
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hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
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hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
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hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
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hwif_cb.ioc_notify_hbfail = bfa_ioc_cb_notify_hbfail;
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hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
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ioc->ioc_hwif = &hwif_cb;
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}
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/**
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* Return true if firmware of current driver matches the running firmware.
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*/
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static bfa_boolean_t
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bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
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{
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return BFA_TRUE;
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}
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static void
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bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
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{
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}
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/**
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* Notify other functions on HB failure.
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*/
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static void
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bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc)
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{
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bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET);
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bfa_reg_read(ioc->ioc_regs.err_set);
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}
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/**
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* Host to LPU mailbox message addresses
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*/
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static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
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{ HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
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{ HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
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};
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/**
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* Host <-> LPU mailbox command/status registers
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*/
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static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
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{ HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
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{ HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
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};
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static void
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bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
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{
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bfa_os_addr_t rb;
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int pcifn = bfa_ioc_pcifn(ioc);
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rb = bfa_ioc_bar0(ioc);
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ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
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ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
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ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
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if (ioc->port_id == 0) {
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ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
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ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
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} else {
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ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
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ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
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}
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/**
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* Host <-> LPU mailbox command/status registers
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*/
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ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
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/*
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* PSS control registers
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*/
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ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
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ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
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ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG);
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ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG);
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/*
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* IOC semaphore registers and serialization
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*/
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ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
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ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
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/**
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* sram memory access
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*/
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ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
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ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
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/*
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* err set reg : for notification of hb failure
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*/
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ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
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}
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/**
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* Initialize IOC to port mapping.
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*/
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static void
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bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
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{
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/**
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* For crossbow, port id is same as pci function.
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*/
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ioc->port_id = bfa_ioc_pcifn(ioc);
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bfa_trc(ioc, ioc->port_id);
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}
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/**
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* Set interrupt mode for a function: INTX or MSIX
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*/
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static void
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bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
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{
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}
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/**
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* Cleanup hw semaphore and usecnt registers
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*/
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static void
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bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
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{
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/*
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* Read the hw sem reg to make sure that it is locked
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* before we clear it. If it is not locked, writing 1
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* will lock it instead of clearing it.
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*/
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bfa_reg_read(ioc->ioc_regs.ioc_sem_reg);
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bfa_ioc_hw_sem_release(ioc);
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}
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bfa_status_t
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bfa_ioc_cb_pll_init(bfa_os_addr_t rb, bfa_boolean_t fcmode)
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{
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u32 pll_sclk, pll_fclk;
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pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN |
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__APP_PLL_212_P0_1(3U) |
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__APP_PLL_212_JITLMT0_1(3U) |
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__APP_PLL_212_CNTLMT0_1(3U);
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pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN |
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__APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) |
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__APP_PLL_400_JITLMT0_1(3U) |
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__APP_PLL_400_CNTLMT0_1(3U);
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bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT);
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bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT);
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bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
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bfa_reg_write(rb + APP_PLL_212_CTL_REG,
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__APP_PLL_212_LOGIC_SOFT_RESET);
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bfa_reg_write(rb + APP_PLL_212_CTL_REG,
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__APP_PLL_212_BYPASS |
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__APP_PLL_212_LOGIC_SOFT_RESET);
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bfa_reg_write(rb + APP_PLL_400_CTL_REG,
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__APP_PLL_400_LOGIC_SOFT_RESET);
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bfa_reg_write(rb + APP_PLL_400_CTL_REG,
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__APP_PLL_400_BYPASS |
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__APP_PLL_400_LOGIC_SOFT_RESET);
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bfa_os_udelay(2);
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bfa_reg_write(rb + APP_PLL_212_CTL_REG,
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__APP_PLL_212_LOGIC_SOFT_RESET);
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bfa_reg_write(rb + APP_PLL_400_CTL_REG,
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__APP_PLL_400_LOGIC_SOFT_RESET);
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bfa_reg_write(rb + APP_PLL_212_CTL_REG,
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pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET);
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bfa_reg_write(rb + APP_PLL_400_CTL_REG,
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pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET);
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bfa_os_udelay(2000);
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bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + APP_PLL_212_CTL_REG), pll_sclk);
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bfa_reg_write((rb + APP_PLL_400_CTL_REG), pll_fclk);
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return BFA_STATUS_OK;
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}
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