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ad68bb9f7a
This is important because on PXA3xx, the physical mapping of SMEMC registers differs from the one on PXA2xx. In order to get PCMCIA working on both PXA2xx and PXA320, the PCMCIA driver was adjusted accordingly as well. Also, various places in the kernel had to be patched to use __raw_read/__raw_write. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
188 lines
8.6 KiB
C
188 lines
8.6 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
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*
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* Taken from pxa-regs.h by Russell King
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*
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* Author: Nicolas Pitre
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PXA2XX_REGS_H
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#define __PXA2XX_REGS_H
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#include <mach/hardware.h>
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/*
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* Power Manager
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*/
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#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
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#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
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#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
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#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
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#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
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#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
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#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
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#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
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#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
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#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
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#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
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#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
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#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
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#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
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#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
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#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
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#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
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#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
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#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
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#define PCMD(x) __REG2(0x40F00080, (x)<<2)
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#define PCMD0 __REG(0x40F00080 + 0 * 4)
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#define PCMD1 __REG(0x40F00080 + 1 * 4)
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#define PCMD2 __REG(0x40F00080 + 2 * 4)
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#define PCMD3 __REG(0x40F00080 + 3 * 4)
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#define PCMD4 __REG(0x40F00080 + 4 * 4)
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#define PCMD5 __REG(0x40F00080 + 5 * 4)
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#define PCMD6 __REG(0x40F00080 + 6 * 4)
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#define PCMD7 __REG(0x40F00080 + 7 * 4)
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#define PCMD8 __REG(0x40F00080 + 8 * 4)
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#define PCMD9 __REG(0x40F00080 + 9 * 4)
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#define PCMD10 __REG(0x40F00080 + 10 * 4)
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#define PCMD11 __REG(0x40F00080 + 11 * 4)
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#define PCMD12 __REG(0x40F00080 + 12 * 4)
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#define PCMD13 __REG(0x40F00080 + 13 * 4)
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#define PCMD14 __REG(0x40F00080 + 14 * 4)
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#define PCMD15 __REG(0x40F00080 + 15 * 4)
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#define PCMD16 __REG(0x40F00080 + 16 * 4)
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#define PCMD17 __REG(0x40F00080 + 17 * 4)
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#define PCMD18 __REG(0x40F00080 + 18 * 4)
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#define PCMD19 __REG(0x40F00080 + 19 * 4)
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#define PCMD20 __REG(0x40F00080 + 20 * 4)
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#define PCMD21 __REG(0x40F00080 + 21 * 4)
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#define PCMD22 __REG(0x40F00080 + 22 * 4)
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#define PCMD23 __REG(0x40F00080 + 23 * 4)
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#define PCMD24 __REG(0x40F00080 + 24 * 4)
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#define PCMD25 __REG(0x40F00080 + 25 * 4)
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#define PCMD26 __REG(0x40F00080 + 26 * 4)
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#define PCMD27 __REG(0x40F00080 + 27 * 4)
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#define PCMD28 __REG(0x40F00080 + 28 * 4)
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#define PCMD29 __REG(0x40F00080 + 29 * 4)
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#define PCMD30 __REG(0x40F00080 + 30 * 4)
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#define PCMD31 __REG(0x40F00080 + 31 * 4)
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#define PCMD_MBC (1<<12)
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#define PCMD_DCE (1<<11)
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#define PCMD_LC (1<<10)
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/* FIXME: PCMD_SQC need be checked. */
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#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
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bit 9 should be 0 all day. */
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#define PVCR_VCSA (0x1<<14)
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#define PVCR_CommandDelay (0xf80)
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#define PCFR_PI2C_EN (0x1 << 6)
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#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
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#define PSSR_RDH (1 << 5) /* Read Disable Hold */
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#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
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#define PSSR_STS (1 << 3) /* Standby Mode Status */
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#define PSSR_VFS (1 << 2) /* VDD Fault Status */
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#define PSSR_BFS (1 << 1) /* Battery Fault Status */
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#define PSSR_SSS (1 << 0) /* Software Sleep Status */
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#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
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#define PCFR_RO (1 << 15) /* RDH Override */
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#define PCFR_PO (1 << 14) /* PH Override */
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#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
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#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
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#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
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#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
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#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
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#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
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#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
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#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
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#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
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#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
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#define RCSR_GPR (1 << 3) /* GPIO Reset */
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#define RCSR_SMR (1 << 2) /* Sleep Mode */
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#define RCSR_WDR (1 << 1) /* Watchdog Reset */
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#define RCSR_HWR (1 << 0) /* Hardware Reset */
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#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
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#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
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#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
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#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
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#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
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#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
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#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
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#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
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#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
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#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
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#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
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#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
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#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
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#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
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#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
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#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
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#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
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#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
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/*
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* PXA2xx specific Core clock definitions
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*/
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#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
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#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
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#define CKEN __REG(0x41300004) /* Clock Enable Register */
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#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
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#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
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#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
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#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
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#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
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#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
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#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
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#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
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#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
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#define CKEN_IM (20) /* Internal Memory Clock Enable */
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#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
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#define CKEN_USIM (18) /* USIM Unit Clock Enable */
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#define CKEN_MSL (17) /* MSL Unit Clock Enable */
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#define CKEN_LCD (16) /* LCD Unit Clock Enable */
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#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
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#define CKEN_I2C (14) /* I2C Unit Clock Enable */
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#define CKEN_FICP (13) /* FICP Unit Clock Enable */
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#define CKEN_MMC (12) /* MMC Unit Clock Enable */
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#define CKEN_USB (11) /* USB Unit Clock Enable */
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#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
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#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
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#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
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#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
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#define CKEN_I2S (8) /* I2S Unit Clock Enable */
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#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
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#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
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#define CKEN_STUART (5) /* STUART Unit Clock Enable */
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#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
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#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
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#define CKEN_SSP (3) /* SSP Unit Clock Enable */
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#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
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#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
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#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
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#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
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#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
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#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
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/* PWRMODE register M field values */
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#define PWRMODE_IDLE 0x1
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#define PWRMODE_STANDBY 0x2
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#define PWRMODE_SLEEP 0x3
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#define PWRMODE_DEEPSLEEP 0x7
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#endif
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