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linux-next/arch/mips/gt64120
Atsushi Nemoto 97dcb82de6 [MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 16:53:08 +00:00
..
common [MIPS] Fix EV64120 and Ocelot builds by providing a plat_timer_setup(). 2006-11-06 20:55:39 +00:00
ev64120 [MIPS] IRQ cleanups 2006-11-30 01:14:46 +00:00
momenco_ocelot [MIPS] Define MIPS_CPU_IRQ_BASE in generic header 2007-02-06 16:53:08 +00:00
wrppmc [MIPS] Define MIPS_CPU_IRQ_BASE in generic header 2007-02-06 16:53:08 +00:00