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fc63efdf4b
The <dt-bindings/pinctrl/omap.h> header file defines a set of macros for different SoCs families that falls under the OMAP sub-arch, that allow to define the padconf register physical address instead of the register offset from the padconf base. But the am43xx and dra7xx SoCs families have their own pinctrl header file so the DTS using these SoCs aren't able to use the AM4372_IOPAD() and DRA7XX_CORE_IOPAD() macros since <dt-bindings/pinctrl/omap.h> is not included. Move the macros to the correct header files so can be used by the DTS. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
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* This header provides constants for DRA pinctrl bindings.
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_DRA_H
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#define _DT_BINDINGS_PINCTRL_DRA_H
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/* DRA7 mux mode options for each pin. See TRM for options */
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#define MUX_MODE0 0x0
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#define MUX_MODE1 0x1
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#define MUX_MODE2 0x2
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#define MUX_MODE3 0x3
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#define MUX_MODE4 0x4
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#define MUX_MODE5 0x5
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#define MUX_MODE6 0x6
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#define MUX_MODE7 0x7
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#define MUX_MODE8 0x8
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#define MUX_MODE9 0x9
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#define MUX_MODE10 0xa
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#define MUX_MODE11 0xb
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#define MUX_MODE12 0xc
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#define MUX_MODE13 0xd
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#define MUX_MODE14 0xe
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#define MUX_MODE15 0xf
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/* Certain pins need virtual mode, but note: they may glitch */
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#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
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#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
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#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
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#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
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#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
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#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
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#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
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#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
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#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
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#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
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#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
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#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
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#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
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#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
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#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
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#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
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#define MODE_SELECT (1 << 8)
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#define PULL_ENA (0 << 16)
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#define PULL_DIS (1 << 16)
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#define PULL_UP (1 << 17)
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#define INPUT_EN (1 << 18)
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#define SLEWCONTROL (1 << 19)
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#define WAKEUP_EN (1 << 24)
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#define WAKEUP_EVENT (1 << 25)
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/* Active pin states */
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#define PIN_OUTPUT (0 | PULL_DIS)
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#define PIN_OUTPUT_PULLUP (PULL_UP)
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#define PIN_OUTPUT_PULLDOWN (0)
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#define PIN_INPUT (INPUT_EN | PULL_DIS)
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#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
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#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
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#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
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/*
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* Macro to allow using the absolute physical address instead of the
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* padconf registers instead of the offset from padconf base.
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*/
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#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
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#endif
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