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59594e13e4
SMC, Static Memory Controller will need more accessors to fine configure its parameters. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
101 lines
3.6 KiB
C
101 lines
3.6 KiB
C
/*
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* arch/arm/mach-at91/include/mach/at91sam9_smc.h
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* Static Memory Controllers (SMC) - System peripherals registers.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9_SMC_H
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#define AT91SAM9_SMC_H
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#include <mach/cpu.h>
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#ifndef __ASSEMBLY__
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struct sam9_smc_config {
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/* Setup register */
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u8 ncs_read_setup;
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u8 nrd_setup;
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u8 ncs_write_setup;
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u8 nwe_setup;
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/* Pulse register */
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u8 ncs_read_pulse;
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u8 nrd_pulse;
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u8 ncs_write_pulse;
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u8 nwe_pulse;
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/* Cycle register */
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u16 read_cycle;
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u16 write_cycle;
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/* Mode register */
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u32 mode;
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u8 tdf_cycles:4;
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};
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extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
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extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
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extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
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extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
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#endif
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#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
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#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
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#define AT91_SMC_NWESETUP_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
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#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
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#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
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#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
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#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
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#define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */
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#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
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#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
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#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
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#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
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#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
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#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
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#define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */
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#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
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#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
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#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
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#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
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#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */
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#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
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#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
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#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
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#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
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#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
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#define AT91_SMC_EXNWMODE_READY (3 << 4)
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#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
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#define AT91_SMC_BAT_SELECT (0 << 8)
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#define AT91_SMC_BAT_WRITE (1 << 8)
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#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
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#define AT91_SMC_DBW_8 (0 << 12)
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#define AT91_SMC_DBW_16 (1 << 12)
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#define AT91_SMC_DBW_32 (2 << 12)
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#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
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#define AT91_SMC_TDF_(x) ((x) << 16)
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#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
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#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
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#define AT91_SMC_PS (3 << 28) /* Page Size */
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#define AT91_SMC_PS_4 (0 << 28)
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#define AT91_SMC_PS_8 (1 << 28)
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#define AT91_SMC_PS_16 (2 << 28)
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#define AT91_SMC_PS_32 (3 << 28)
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#endif
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